UJA1066TW/5V0,518 NXP Semiconductors, UJA1066TW/5V0,518 Datasheet - Page 42

• Manufacturer Part Number: UJA1066TW/5V0,518
• Manufacturer: NXP Semiconductors

Specifications of UJA1066TW/5V0,518

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Standard Supported: ISO 11898-2
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
7. Limiting values
Table 25.
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.
UJA1066_2
Product data sheet
Symbol
V
V
BAT42
BAT14
Limiting values
Parameter
BAT42 supply voltage
BAT14 supply voltage
6.13.2 Forced normal mode
To remain in Software development mode the SDM bit in the Mode register must be set
each time the Mode register is accessed (i.e. watchdog triggering) regardless of how
Software development mode was entered.
Software development mode can be exited at any time by clearing the SDM bit in the
Mode register. Reentering the Software development mode is only possible by
reconnecting the battery supply (pin BAT42), thereby forcing a new power-on reset.
The UJA1066 provides Forced normal mode for system evaluation purposes. This mode
is strictly for evaluation purposes only. In this mode the characteristics as defined in
Section 9
In Forced normal mode the SBC behaves as follows:
Forced normal mode is activated by applying the correct V
TEST pin during initial battery connection.
•
•
•
•
•
•
•
•
•
•
•
•
•
SPI access (writing and reading) is blocked
Watchdog disabled
Interrupt monitoring disabled
Reset monitoring disabled
Reset lengthening disabled
All transitions to Fail-safe mode are disabled, except a V1 undervoltage for more than
t
V1 is started with the long reset time t
is performed until V1 is restored (normal behavior), and the SBC stays in Forced
normal mode; if an overload occurs at V1 lasting longer than t
is entered
V2 is on; overload protection active
V3 is on; overload protection active
CAN is in Active mode and cannot switch to Off-line mode
INH/LIMP pin is HIGH
SYSINH is HIGH
EN pin at same level as RSTN pin
V1(CLT)
and
Section 10
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 17 March 2010
cannot be guaranteed.
Conditions
load dump; t ≤ 500 ms
V
BAT42
continuous
load dump; t ≤ 500 ms
≥ V
BAT14
− 1 V
RSTNL
High-speed CAN fail-safe system basis chip
. In the case of a V1 undervoltage, a reset
Min
−0.3
-
−0.3
-
th(TEST)
V1(CLT)
input voltage at the
Max
+60
+60
+33
+45
UJA1066
© NXP B.V. 2010. All rights reserved.
, Fail-safe mode
42 of 70
Unit
V
V
V
V