UJA1066TW/5V0,518 NXP Semiconductors, UJA1066TW/5V0,518 Datasheet - Page 26

• Manufacturer Part Number: UJA1066TW/5V0,518
• Manufacturer: NXP Semiconductors

Specifications of UJA1066TW/5V0,518

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Standard Supported: ISO 11898-2
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 4.
UJA1066_2
Product data sheet
Register
address bits
(A1, A0)
00
01
10
11
Register overview
6.12.1 SPI register mapping
6.12.2 Register overview
all modes
Normal mode;
Normal mode;
Operating
mode
Standby mode;
Flash mode
Start-up mode;
Restart mode
Standby mode
Start-up mode;
Restart mode;
Flash mode
Normal mode;
Standby mode
Start-up mode;
Restart mode;
Flash mode
To protect against wrong or illegal SPI instructions, the SBC detects the following SPI
failures:
Any control bit that can be set by software can be read by the application. This facilitates
software debugging and allows control algorithms to be implemented.
Watchdog serving and mode setting are performed within the same access cycle; this
allows an SBC mode change to occur only while serving the watchdog.
Each register contains 12 data bits; the other 4 bits are used for register selection and
read/write definition.
The SPI interface provides access to all SBC registers; see
and A0) of the message header define the register address. The third bit is the read
register select bit (RRS) used to select one of two feedback registers. The fourth bit (RO)
allows ‘read-only’ access to one of the feedback registers. Which of the SBC registers can
be accessed also depends on the SBC operating mode.
•
•
•
SPI clock count failure (wrong number of clock cycles during one SPI access): only
16 clock periods are allowed during an SCS cycle. Any deviation from the 16 clock
cycles results in an SPI failure interrupt, if enabled. The access is ignored by the SBC.
In Start-up and Restart modes, a reset is forced instead of an interrupt.
Forbidden mode changes according to
Illegal Mode register code. Undefined operating mode or watchdog period coding
results in an immediate system reset; see
Write access (RO = 0)
Mode register
Interrupt Enable register
Special Mode register
System Configuration
register
General Purpose register 0
Physical Layer Control
register
General Purpose register 1
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Rev. 03 — 17 March 2010
Read access (RO = 0 or RO = 1)
Read Register Select
(RRS) bit = 0
System Status register
Interrupt Enable Feedback
register
Interrupt Enable Feedback
register
System Configuration
Feedback register
System Configuration
Feedback register
Physical Layer Control
Feedback register
Physical Layer Control
Feedback register
High-speed CAN fail-safe system basis chip
Figure 3
Section
result in an immediate system reset
6.12.3.
Table
Read Register Select
(RRS) bit = 1
System Diagnosis register
Interrupt register
Special Mode Feedback
register
General Purpose Feedback
register 0
General Purpose Feedback
register 0
General Purpose Feedback
register 1
General Purpose Feedback
register 1
4. The first two bits (A1
UJA1066
© NXP B.V. 2010. All rights reserved.
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