UJA1066TW/5V0,518 NXP Semiconductors, UJA1066TW/5V0,518 Datasheet - Page 15

• Manufacturer Part Number: UJA1066TW/5V0,518
• Manufacturer: NXP Semiconductors

Specifications of UJA1066TW/5V0,518

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Standard Supported: ISO 11898-2
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
UJA1066_2
Product data sheet
6.5.1 RSTN pin
6.5 System reset
If the microcontroller supply current rises above I
watchdog will be restarted using the watchdog period last used and, if enabled, a
watchdog restart interrupt will be generated.
In the case of a direct mode change to Standby with watchdog OFF selected, the longest
possible watchdog period is used. It should be noted that V1 current monitoring is not
active in Sleep mode.
The reset function of the UJA1066 provides two signals to deal with reset events:
The system reset pin (RSTN) is a bidirectional input/output. RSTN is active LOW with a
selectable pulse length triggered by the following events (see
The source of the reset event can be determined by reading the RSS[3:0] bits in the
System Status registers.
The SBC will lengthen a reset event, to 1 ms or 20 ms, to ensure that external hardware is
properly reset. When the battery is connected initially, a short power-on reset of 1 ms is
generated once voltage V1 is present. Once started, the microcontroller can set the Reset
Length Control (RLC) bit in the System Configuration register; this allows the reset pulse
to be adjusted for future reset events. When this bit is set, reset events are lengthened to
20 ms. Fail-safe behavior ensures that this bit is set automatically (to 20 ms) in Restart
and Fail-safe modes. This mechanism guarantees that an erroneously shortened reset
pulse will still restart the microcontroller, at least within the second trial period by using the
long reset pulse.
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RSTN; the global ECU system reset
EN; a fail-safe global enable signal
Power-on (first battery connection) or V
Low V1 supply
V1 current above threshold in Standby mode while watchdog OFF behavior is
selected
V3 is down due to short-circuit condition in Sleep mode
RSTN externally forced LOW, falling edge event
Successful preparation for Flash mode completed
Successful exit from Flash mode
Wake-up from Standby mode via pins CAN or WAKE if programmed accordingly, or
any wake-up event from Sleep mode
Wake-up event from Fail-safe mode
Watchdog trigger failure (too early, overflow, wrong code)
Illegal mode code applied via SPI
Interrupt not served within t
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 17 March 2010
RSTN(INT)
High-speed CAN fail-safe system basis chip
BAT42
thH(V1)
below power-on reset threshold voltage
while the watchdog is OFF, the
Figure
3):
UJA1066
© NXP B.V. 2010. All rights reserved.
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