UJA1066TW/5V0,518 NXP Semiconductors, UJA1066TW/5V0,518 Datasheet - Page 9

• Manufacturer Part Number: UJA1066TW/5V0,518
• Manufacturer: NXP Semiconductors

Specifications of UJA1066TW/5V0,518

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Standard Supported: ISO 11898-2
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
UJA1066_2
Product data sheet
6.2.1 Start-up mode
6.2.2 Restart mode
6.2.3 Fail-safe mode
6.2.4 Normal mode
Start-up mode is the ‘home page’ of the SBC. This mode is entered when battery and
ground are connected for the first time. Start-up mode is also entered after any event that
results in a system reset. The reset source information is provided by the SBC to support
software initialization cycles that depend on the reset event.
It is also possible to enter Start-up mode via a wake-up from Standby mode, Sleep mode
or Fail-safe mode. Such a wake-up event can be triggered in the CAN-bus or by the local
WAKE pin.
A lengthened reset time, t
either user-defined (via the RLC bit in the System Configuration register; see
Table
SBC during the reset lengthening time.
When the reset time has elapsed (pin RSTN is released and goes HIGH) the watchdog
timer will wait to be initialized. If the watchdog initialization is successful, the selected
operating mode (Normal mode or Flash mode) will be entered. Otherwise the SBC will
enter Restart mode.
The purpose of Restart mode is to give the application a second chance to start up,
should the first attempt from Start-up mode fail. Entering Restart mode will always set the
reset lengthening time t
maximum reset length, regardless of previous events.
If start-up from Restart mode is successful (the earlier problems do not recur and
watchdog initialization is successful), the SBC will enter Normal mode (see
problems persist or if V1 fails to start up, the SBC will enter Fail-safe mode.
Severe fault situations will cause the SBC to enter Fail-safe mode. Fail-safe mode is also
entered if start-up from Restart mode fails. Fail-safe mode offers the lowest possible
system power consumption from the SBC and from the external components controlled by
the SBC.
A wake-up (via the CAN-bus or the WAKE pin) is needed to leave Fail-safe mode. This is
only possible if the on-chip oscillator is running correctly. The SBC restarts from Fail-safe
mode with a defined delay, t
mode. Regulator V1 will restart and t
Section
Normal mode gives access to all SBC system resources, including CAN, INH/LIMP and
EN. The SBC watchdog runs in (programmable) Window mode to guarantee the strictest
software supervision. A system reset is performed whenever the watchdog is not being
properly served.
Interrupts from the SBC to the host microcontroller are also monitored. A system reset is
performed if the host microcontroller does not respond within t
27) or defaults to the value given in
6.5.1).
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 17 March 2010
RSTNL
RSTNL
ret
to the higher value (see
, to guarantee a discharged V1 before entering Start-up
, is observed on entering Start-up mode. This reset time is
RSTNL
Section
High-speed CAN fail-safe system basis chip
will be set to the higher value (see
6.12.12. Pin RSTN is held LOW by the
Table
27) to guarantee the
RSTN(INT)
UJA1066
.
© NXP B.V. 2010. All rights reserved.
Figure
Table 11
3). If
9 of 70
and