UJA1066TW/5V0,518 NXP Semiconductors, UJA1066TW/5V0,518 Datasheet - Page 23

• Manufacturer Part Number: UJA1066TW/5V0,518
• Manufacturer: NXP Semiconductors

Specifications of UJA1066TW/5V0,518

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Standard Supported: ISO 11898-2
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
UJA1066_2
Product data sheet
Fig 10. States of the INH/LIMP pin
6.7.4.3 GND shift detection
6.8 Inhibit and limp-home output
6.9 Wake-up input
INH/LIMP:
ILEN = 1
ILC = 1
HIGH
The SBC can detect ground shifts in reference to the CAN-bus. Two different ground shift
detection levels can be selected with the GSTHC bit in the Configuration register. The
failure can be read out in the System Diagnosis register. Any detected or recovered GND
shift event is signalled via a GSI an interrupt, if enabled.
The INH/LIMP output pin is a 3-state output, which can be used either as an inhibit for an
extra (external) voltage regulator or as a ‘limp-home’ output. The pin is controlled via bits
ILEN and ILC in the System Configuration register; see
When pin INH/LIMP is used as an inhibit output, a pull-down resistor to GND ensures a
default LOW level. The pin can be set HIGH according to the state diagram.
When pin INH/LIMP is used as limp-home output, a pull-up resistor to V
default HIGH level. The pin is automatically set LOW when the SBC enters Fail-safe
mode.
The WAKE input comparator is triggered by negative edges on pin WAKE. Pin WAKE has
an internal pull-up resistor to BAT42. It can be operated in two sampling modes, which are
selected via the WAKE Sample Control bit (WSC in
•
•
state change via SPI
Continuous sampling (with an internal clock) if the bit is set
Sampling synchronized to the cyclic behavior of V3 if the bit is cleared; see
This is to minimize bias current in the external switches during low-power operation.
Two repetition times are possible, 16 ms and 32 ms.
power-on
OR (enter Start-up mode after
wake-up reset, external reset
OR enter Restart mode
OR enter Sleep mode
state change via SPI
or V1 undervoltage)
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 17 March 2010
OR enter Fail-safe mode
state change via SPI
state change via SPI
INH/LIMP:
floating
ILC = 1/0
ILEN = 0
OR enter Fail-safe mode
state change via SPI
High-speed CAN fail-safe system basis chip
state change via SPI
Table
Figure
001aad178
11):
INH/LIMP:
10.
ILEN = 1
ILC = 0
LOW
UJA1066
© NXP B.V. 2010. All rights reserved.
BAT42
ensures a
Figure
23 of 70
11.