UJA1066TW/5V0,518 NXP Semiconductors, UJA1066TW/5V0,518 Datasheet - Page 41

• Manufacturer Part Number: UJA1066TW/5V0,518
• Manufacturer: NXP Semiconductors

Specifications of UJA1066TW/5V0,518

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Standard Supported: ISO 11898-2
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 22.
Table 23.
Table 24.
UJA1066_2
Product data sheet
Symbol
ISDM
ERREM
WDPRE
V1RTHC
Symbol
DIC
GP0[10:7]
GP0[6:0]
Symbol
GP1[11:0]
Special Mode register: status at reset
General Purpose register 0 and General Purpose Feedback register 0: status at reset
General Purpose register 1 and General Purpose Feedback register 1: status at reset
Name
initialize software development mode
error pin emulation mode
watchdog prescale factor
V1 reset threshold control
Name
device identification control
general purpose bits 10 to 7 (version)
general purpose bits 6 to 0 (SBC type)
Name
general purpose bits 11 to 0
6.13.1 Software development mode
6.13 Test modes
The Software development mode is intended to support software developers in writing
and pretesting application software without having to work around watchdog triggering
and without unwanted jumps to Fail-safe mode.
In Software development mode, the following events do not force a system reset:
However, in the case of a watchdog trigger failure the reset source information is still
written to the System Status register, as if a real reset event had occurred.
The exclusion of watchdog related resets allows for simplified software testing because
problems with watchdog triggering can be indicated by interrupts instead of resets. The
SDM bit does not affect the watchdog behavior in Standby and Sleep modes. This allows
the cyclic wake-up behavior to be evaluated in these modes.
All transitions to Fail-safe mode are disabled. This makes it possible to work with an
external emulator that clamps the reset line LOW in debugging mode. A V1 undervoltage
of more than t
protect the SBC). Transitions from Start-up mode to Restart mode are still possible.
There are two ways to enter Software development mode. One is by setting the ISDM bit
in the Special Mode register
battery while the SBC is in Start-up mode. The other is by applying the correct V
input voltage at pin TEST before the battery has been connected to pin BAT42.
•
•
•
•
Watchdog overflow in Normal mode
Watchdog window miss
Interrupt time-out
Elapsed start-up time
V1(CLT)
All information provided in this document is subject to legal disclaimers.
is the only exception that results in a transition to Fail-safe mode (to
Rev. 03 — 17 March 2010
0 (no)
0 (EN function)
00 (factor 1)
00 (90 %)
0 (device ID)
000 0110 (UJA1066) no change
0000 0000 0000
Power-on
Power-on
mask version
Power-on
(Table
13); possible only after the initial connection of a
High-speed CAN fail-safe system basis chip
no change
no change
no change
no change
no change
no change
no change
Start-up
Start-up
Start-up
no change
no change
no change
00 (90 %)
no change
no change
no change
Restart
Restart
no change
Restart
UJA1066
© NXP B.V. 2010. All rights reserved.
th(TEST)
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