NP5Q128A13ESFC0E Micron Technology Inc, NP5Q128A13ESFC0E Datasheet - Page 12

• Manufacturer Part Number: NP5Q128A13ESFC0E
• Manufacturer: Micron Technology Inc

Specifications of NP5Q128A13ESFC0E

• Lead Free Status / RoHS Status: Supplier Unconfirmed

3
12/56
CS3
SPI interface with
(CPOL, CPHA) =
SPI Bus Master
(0, 0) or (1, 1)
CS2 CS1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
bus master is in standby mode and not transferring data:
Figure 3.
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 3
one device is selected at a time, so only one device drives the serial data output (DQ1) line
at a time, the other devices are high impedance. Resistors R (represented in
ensure that the Omneo™ P5Q PCM is not selected if the bus master leaves the S line in the
high impedance state. As the bus master may enter a state where all inputs/outputs are in
high impedance at the same time (for example, when the bus master is reset), the clock line
(C) must be connected to an external pull-down resistor so that, when all inputs/outputs
become high impedance, the S line is pulled High while the C line is pulled Low (thus
ensuring that S and C do not become High at the same time, and so, that the t
requirement is met). The typical value of R is 100 kΩ, assuming that the time constant R*C
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
shows an example of three devices connected to an MCU, on an SPI bus. Only
SDO
SDI
SCK
R
Bus master and memory devices on the SPI bus
R
C
S
DQ1DQ0
SPI memory
device
W
V
CC
HOLD
V
R
SS
C
S
DQ1 DQ0
SPI memory
device
Figure
W
V
HOLD
CC
4, is the clock polarity when the
R
V
SS
C
S
DQ1DQ0
SPI memory
device
W
Figure
V
SHCH
CC
HOLD
AI13725b
V
V
V
SS
3)
CC
SS
p