NP5Q128A13ESFC0E Micron Technology Inc, NP5Q128A13ESFC0E Datasheet - Page 42

• Manufacturer Part Number: NP5Q128A13ESFC0E
• Manufacturer: Micron Technology Inc

Specifications of NP5Q128A13ESFC0E

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.14
42/56
Bulk erase (BE)
The bulk erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a write
enable (WREN) instruction must previously have been executed. After the write enable
(WREN) instruction has been decoded, the device sets the write enable latch (WEL).
The bulk erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on serial data input (DQ0). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the bulk erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed bulk erase cycle (whose duration is t
bulk erase cycle is in progress, the status register may be read to check the value of the
write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed bulk
erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the write enable latch (WEL) bit is reset. RDSR is the only instruction accepted
while device is busy with erase operation; all other instructions are ignored.
The bulk erase (BE) instruction is executed only if all block protect (BP3, BP2, BP1, BP0)
bits are 0. The bulk erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 19. Bulk erase (BE) instruction sequence
S
C
DQ0
Figure
0
1
2
19.
Instruction
3
4
5
6
7
BE
AI13743
) is initiated. While the