NP5Q128A13ESFC0E Micron Technology Inc, NP5Q128A13ESFC0E Datasheet - Page 25

• Manufacturer Part Number: NP5Q128A13ESFC0E
• Manufacturer: Micron Technology Inc

Specifications of NP5Q128A13ESFC0E

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.2
Write disable (WRDI)
The write disable (WRDI) instruction
The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The write enable latch (WEL) bit is reset under the following conditions:
Figure 7.
– Power-up
– Write disable (WRDI) instruction completion
– Write status register (WRSR) instruction completion
– Page program (PP) instruction completion
– Dual input fast program (DIFP) instruction completion
– Quad input fast program (QIFP) instruction completion
– Sector erase (SE) instruction completion
– Bulk erase (BE) instruction completion
Write disable (WRDI) instruction sequence
S
C
DQ0
DQ1
High Impedance
(Figure
0
1
2
Instruction
7) resets the write enable latch (WEL) bit.
3
4
5
6
7
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