NP5Q128A13ESFC0E Micron Technology Inc, NP5Q128A13ESFC0E Datasheet - Page 43

• Manufacturer Part Number: NP5Q128A13ESFC0E
• Manufacturer: Micron Technology Inc

Specifications of NP5Q128A13ESFC0E

• Lead Free Status / RoHS Status: Supplier Unconfirmed

7
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V
A safe configuration is provided in
To avoid data corruption and inadvertent write operations during power-up, a power on reset
(POR) circuit is included. The logic inside the device is held reset while V
power on reset (POR) threshold voltage, V
does not respond to any instruction.
Moreover, the device ignores all write enable (WREN), page program (PP), dual input fast
program (DIFP), sector erase (SE), bulk erase (BE), write status register (WRSR)
instructions until a time delay of t
the V
time, V
should be sent until the later of:
These values are specified in
If the time, t
for read instructions even if the t
After power-up, the device is in the following state:
Normal precautions must be taken for supply line decoupling, to stabilize the V
Each device in a system should have the V
to the package pins (generally, this capacitor is of the order of 100 nF).
At power-down, when V
(POR) threshold voltage, V
to any instruction (the designer needs to be aware that if power-down occurs while a write,
program or erase cycle is in progress, some data corruption may result).
– V
– V
– t
– t
– The device is in the standby power mode
– The write enable latch (WEL) bit is reset
– The write in progress (WIP) bit is reset
WI
CC
PUW
VSL
CC
SS
threshold. However, the correct operation of the device is not guaranteed if, by this
is still below V
(min) at power-up, and then for a further delay of t
at power-down.
after V
VSL
after V
, has elapsed, after V
CC
CC
has passed the V
has passed the V
CC
CC
WI
(min). No write status register, program, erase instructions
drops from the operating voltage, to below the power on reset
, all operations are disabled and the device does not respond
Table
CC
PUW
PUW
until V
Section 3: SPI
9.
CC
delay has not yet fully elapsed.
has elapsed after the moment that V
CC
WI
rises above V
CC
(min) level.
threshold
WI
CC
reaches the correct value:
– all operations are disabled, and the device
line decoupled by a suitable capacitor close
modes.
CC
(min), the device can be selected
VSL
CC
CC
is less than the
rises above
CC
supply.
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