NP5Q128A13ESFC0E Micron Technology Inc, NP5Q128A13ESFC0E Datasheet - Page 32

• Manufacturer Part Number: NP5Q128A13ESFC0E
• Manufacturer: Micron Technology Inc

Specifications of NP5Q128A13ESFC0E

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.7
32/56
Read data bytes at higher speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the read
data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address
A[23:0] and a dummy byte, each bit being latched-in during the rising edge of Serial Clock
(C). Then the memory contents, at that address, are shifted out on serial data output (DQ1)
at a maximum frequency f
The instruction sequence is shown in
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single read data bytes at higher speed (FAST_READ) instruction.
When the highest address is reached, the address counter rolls over to 000000h, allowing
the read sequence to be continued indefinitely.
The read data bytes at higher speed (FAST_READ) instruction is terminated by driving Chip
Select (S) High. Chip Select (S) can be driven High at any time during data output. Any read
data bytes at higher speed (FAST_READ) instruction, while an erase, program, write cycle
is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 12. Read data bytes at higher speed (FAST_READ) instruction sequence
DQ0
DQ1
S
C
DQ0
DQ1
S
C
and data-out sequence
7
0
32 33 34
1
6
High Impedance
Dummy byte
5
2
Instruction
3
4
35
C
3
4
36 37 38 39 40 41 42 43 44 45 46
, during the falling edge of Serial Clock (C).
5
2
1
6
7
0
MSB
23
7
8
Figure
22 21
9 10
6
24-bit address
DATA OUT 1
5
12.
4
3
28 29 30 31
3
2
2
(1)
1
1
0
0
47
MSB
7
6
DATA OUT 2
5
4
3
2
1
0
MSB
AI13737b
7