NP5Q128A13ESFC0E Micron Technology Inc, NP5Q128A13ESFC0E Datasheet - Page 28

• Manufacturer Part Number: NP5Q128A13ESFC0E
• Manufacturer: Micron Technology Inc

Specifications of NP5Q128A13ESFC0E

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.4.4
6.4.5
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Top/bottom bit
The top/bottom (TB) bit is non-volatile. It can be set and reset with the write status register
(WRSR) instruction provided that the write enable (WREN) instruction has been issued. The
top/bottom (TB) bit is used in conjunction with the block protect (BP0, BP1, BP2, BP3) bits
to determine if the protected area defined by the block protect bits starts from the top or the
bottom of the memory array:
The top/bottom bit cannot be written when the SRWD bit is set to ‘1’ and the W pin is driven
Low.
SRWD bit
The status register write disable (SRWD) bit is operated in conjunction with the write protect
(W) signal. The status register write disable (SRWD) bit and the write protect (W) signal
allow the device to be put in the hardware protected mode (when the status register write
disable (SRWD) bit is set to ‘1’, and write protect (W) is driven Low). In this mode, the non-
volatile bits of the status register (SRWD, TB, BP3, BP2, BP1, BP0) become read-only bits
and the write status register (WRSR) instruction is no longer accepted for execution.
Figure 9.
S
C
DQ0
DQ1
– When top/bottom bit is reset to ‘0’ (default value), the area protected by the block
– When top/bottom bit is set to ‘1’, the area protected by the block protect bits starts
protect bits starts from the top of the memory array (see
sizes)
from the bottom of the memory array (see
Read status register (RDSR) instruction sequence and data-out sequence
0
High Impedance
1
2
Instruction
3
4
5
6
7
MSB
7
8
6
9 10 11 12 13 14 15
Status register out
5
4
3
Table 2: Protected area
2
1
0
MSB
7
6
Table 2: Protected area
Status register out
5
4
3
sizes).
2
1
0
7
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