NP5Q128A13ESFC0E Micron Technology Inc, NP5Q128A13ESFC0E Datasheet - Page 15

• Manufacturer Part Number: NP5Q128A13ESFC0E
• Manufacturer: Micron Technology Inc

Specifications of NP5Q128A13ESFC0E

• Lead Free Status / RoHS Status: Supplier Unconfirmed

4.4
4.5
4.6
4.7
Sector erase and bulk erase
A sector can be erased to all 1s (FFh) at a time using the sector erase (SE) instruction. The
entire memory can be erased using the bulk erase (BE) instruction. This starts an internal
erase cycle (of duration t
The erase instruction must be preceded by a write enable (WREN) instruction.
Polling during a write, program or erase cycle
A further improvement in the time to write status register (WRSR), page program (PP), dual
input fast program (DIFP), quad input fast program (QIFP), or erase (SE or BE) can be
achieved by not waiting for the worst case delay (t
in progress (WIP) bit is provided in the status register so that the application program can
monitor its value, polling it to establish when the previous write cycle, program cycle, or
erase cycle is complete.
Active power and standby power
When Chip Select (S) is Low, the device is selected, and in the active power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the active power
mode until all internal cycles have completed (program, erase, write status register). The
device then goes in to the standby power mode. The device consumption drops to I
Status register
The status register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See
detailed description of the status register bits.
SE
or t
BE
).
Section 6.4: Read status register (RDSR)
W
, t
PP
, t
SMEN
, t
SMEX
, t
SE
, or t
BE
). The write
CC1
for a
15/56
.