NP5Q128A13ESFC0E Micron Technology Inc, NP5Q128A13ESFC0E Datasheet - Page 30

• Manufacturer Part Number: NP5Q128A13ESFC0E
• Manufacturer: Micron Technology Inc

Specifications of NP5Q128A13ESFC0E

• Lead Free Status / RoHS Status: Supplier Unconfirmed

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Table 8.
1. As defined by the values in the block protect (BP3, BP2, BP1, BP0) bits of the status register, as shown in
The protection features of the device are summarized in
When the status register write disable (SRWD) bit of the status register is 0 (its initial
delivery state), it is possible to write to the status register provided that the write enable latch
(WEL) bit has previously been set by a write enable (WREN) instruction, regardless of the
whether Write Protect (W) is driven High or Low.
When the status register write disable (SRWD) bit of the status register is set to ‘1’, two
cases need to be considered, depending on the state of Write Protect (W):
Regardless of the order of the two events, the hardware protected mode (HPM) can be
entered:
The only way to exit the hardware protected mode (HPM) once entered is to pull Write
Protect (W) High.
Table
– If Write Protect (W) is driven High, it is possible to write to the status register provided
– If write protect (W) is driven Low, it is not possible to write to the status register even if
– by setting the status register write disable (SRWD) bit after driving Write Protect (W)
– or by driving Write Protect (W) Low after setting the status register write disable
W
1
0
1
0
that the write enable latch (WEL) bit has previously been set by a write enable
(WREN) instruction.
the write enable latch (WEL) bit has previously been set by a write enable (WREN)
instruction (attempts to write to the status register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the block protect (BP3, BP2, BP1, BP0) bits of the
status register, are also hardware protected against data modification.
Low
(SRWD) bit.
2.
Protection modes
SRWD
bit
0
0
1
1
Hardware
protected
protected
Software
(SPM)
(HPM)
Mode
Write protection of
Status register is
writable (if the
WREN instruction
has set the WEL
bit)
The values in the
SRWD, TB, BP3,
BP2, BP1 and BP0
bits can be
changed
Status register is
hardware write
protected
The values in the
SRWD, TB, BP3,
BP2, BP1 and BP0
bits cannot be
changed
the status register
Protected against
page program,
sector erase, and
bulk erase
Protected against
page program,
sector erase, and
bulk erase
Protected area
Table
8.
Memory content
(1)
Ready to accept
page program, and
sector erase
instructions
Ready to accept
page program, and
sector erase
instructions
Unprotected area
(1)