NP5Q128A13ESFC0E Micron Technology Inc, NP5Q128A13ESFC0E Datasheet - Page 37

• Manufacturer Part Number: NP5Q128A13ESFC0E
• Manufacturer: Micron Technology Inc

Specifications of NP5Q128A13ESFC0E

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.11
Note:
Dual input fast program (DIFP)
This definition applies to all flavors of Dual input fast program: Legacy Program, Bit-
alterable Write and Program on all 1s.
The dual input fast program (DIFP) instruction is very similar to the page program (PP)
instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of
only one. Inputting the data on two pins instead of one doubles the data transfer bandwidth
compared to the page program (PP) instruction.
The dual input fast program (DIFP) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes and at least one data byte on serial
data input (DQ0).
If the 6 least significant address bits (A5-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 6 least significant bits (A5-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
If more than 64 bytes are sent to the device, previously latched data are discarded and the
last 64 data bytes are guaranteed to be programmed/written correctly within the same page.
If less than 64 data bytes are sent to device, they are correctly programmed/written at the
requested addresses without having any effects on the other bytes in the same page. (With
Program on all 1s, the entire page should already have been set to all 1s (FFh).)
For optimized timings, it is recommended to use the dual input fast program (DIFP)
instruction to program all consecutive targeted bytes in a single sequence rather to using
several dual input fast program (DIFP) sequences each containing only a few bytes (see
Table 16: AC
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the dual input fast program (DIFP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose
duration is t
status register may be read to check the value of the write in progress (WIP) bit. The write in
progress (WIP) bit is 1 during the self-timed page program cycle, and 0 when it is
completed. At some unspecified time before the cycle is completed, the write enable latch
(WEL) bit is reset. RDSR is the only instruction accepted while a dual input fast program
operation is in progress; all other instructions are ignored.
A dual input fast program (DIFP) instruction applied to a page that is protected by the block
protect (BP3, BP2, BP1, BP0) bits (see
PP
characteristics).
) is initiated. While the dual input fast program (DIFP) cycle is in progress, the
Figure
Table
16.
2) is not executed.
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