NP5Q128A13ESFC0E Micron Technology Inc, NP5Q128A13ESFC0E Datasheet - Page 41

• Manufacturer Part Number: NP5Q128A13ESFC0E
• Manufacturer: Micron Technology Inc

Specifications of NP5Q128A13ESFC0E

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.13
Sector erase (SE)
The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it
can be accepted, a write enable (WREN) instruction must previously have been executed.
After the write enable (WREN) instruction has been decoded, the device sets the write
enable latch (WEL).
The sector erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on serial data input (DQ0). Any address inside the
sector (see
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the sector erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed sector erase cycle (whose duration is t
initiated. While the sector erase cycle is in progress, the status register may be read to
check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during
the self-timed sector erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the write enable latch (WEL) bit is reset. RDSR is the only
instruction accepted while device is busy with erase operation; all other instructions are
ignored.
A sector erase (SE) instruction applied to a page which is protected by the block protect
(BP3, BP2, BP1, BP0) bits (see
Figure 18. Sector erase (SE) instruction sequence
Table
S
C
DQ1
3) is a valid address for the sector erase (SE) instruction. Chip Select (S)
0
1
Table 2
2
Instruction
3
Figure
4
and
5
6
Table
18.
7
MSB
23 22
8
3) is not executed.
9
24-bit address
2
29 30 31
(1)
1
0
AI13742b
SE
) is
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