NP5Q128A13ESFC0E Micron Technology Inc, NP5Q128A13ESFC0E Datasheet - Page 27

• Manufacturer Part Number: NP5Q128A13ESFC0E
• Manufacturer: Micron Technology Inc

Specifications of NP5Q128A13ESFC0E

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.4
6.4.1
6.4.2
6.4.3
Read status register (RDSR)
The read status register (RDSR) instruction allows the status register to be read. The status
register may be read at any time, even while a program, erase, write status register cycle is
in progress. When one of these cycles is in progress, it is recommended to check the write
in progress (WIP) bit before sending a new instruction to the device. It is also possible to
read the status register continuously, as shown in
RDSR is the only instruction accepted by the device while a program, erase, write status
register operation is in progress.
Table 7.
The status and control bits of the status register are as follows:
WIP bit
The write in progress (WIP) bit indicates whether the memory is busy with a write status
register, program, erase cycle. When set to ‘1’, such a cycle is in progress, when reset to ‘0’
no such cycle is in progress.
While WIP is ‘1’, RDSR is the only instruction the device will accept; all other instructions are
ignored.
WEL bit
The write enable latch (WEL) bit indicates the status of the internal write enable latch. When
set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write enable latch is
reset and no write status register, program, erase instruction is accepted.
BP3, BP2, BP1, BP0 bits
The block protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the
area to be software protected against program (or write) and erase instructions. These bits
are written with the write status register (WRSR) instruction. When one or more of the block
protect (BP3, BP2, BP1, BP0) bits is set to ‘1’, the relevant memory area (as defined in
Table
(DIFP),quad input fast program (QIFP), and sector erase (SE) instructions. The block
protect (BP3, BP2, BP1, BP0) bits can be written provided that the hardware protected
mode has not been set.The bulk erase (BE) instruction is executed if, and only if, all block
protect (BP3, BP2, BP1, BP0) bits are 0.
Status register write protect
SRWD
2) becomes protected against page program (PP), dual input fast program
b7
Status register format
BP3
Top/bottom bit
TB
BP2
Block protect bits
Figure
BP1
9.
Write enable latch bit
BP0
WEL
Write in progress bit
WIP
b0
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