N25Q128A11B1240E NUMONYX, N25Q128A11B1240E Datasheet - Page 113

• Manufacturer Part Number: N25Q128A11B1240E
• Manufacturer: NUMONYX

Specifications of N25Q128A11B1240E

• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 7ns
• Interface Type: Serial (SPI)
• Boot Type: Bottom
• Address Bus: 1b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: TBGA
• Program/erase Volt (typ): 1.7 to 2/8.5 to 9.5V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 8b
• Number Of Words: 16M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / Rohs Status: Supplier Unconfirmed

9.2
S
C
DQ0
DQ1
Figure 43. Release from Deep Power-down instruction sequence
DIO-SPI Instructions
In DIO-SPI protocol, instructions, addresses and input/Output data always run in parallel on
two wires: DQ0 and DQ1.
In the case of a Dual Command Fast Read (DCFR), Read OTP (ROTP), Read Lock
Registers (RDLR), Read Status Register (RDSR), Read Flag Status Register (RFSR), Read
NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR),
Read Volatile Enhanced Configuration Register (RDVECR) and Read Identification (RDID)
instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip
Select (S) can be driven High after any bit of the data-out sequence is being shifted out.
In the case of a Dual Command Page Program (DCPP), Program OTP (POTP), Subsector
Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Program/Erase Suspend (PES),
Program/Erase Resume (PER), Write Status Register (WRSR), Clear Flag Status Register
(CLFSR), Write to Lock Register (WRLR), Write Configuration Register (WRVCR), Write
Enhanced Configuration Register (WRVECR), Write NV Configuration Register
(WRNVCR), Write Enable (WREN) or Write Disable (WRDI) instruction, Chip Select (S)
must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is
not executed.
All attempts to access the memory array during a Write Status Register cycle, a Write Non
Volatile Configuration Register, a Program cycle or an Erase cycle are ignored, and the
internal Write Status Register cycle, Write Non Volatile Configuration Register, Program
cycle or Erase cycle continues unaffected, the only exception is the Program/Erase
Suspend instruction (PES), that can be used to pause all the program and the erase cycles
but the Program OTP (POT),, Bulk Erase (BE) and Write Non Volatile Configuration
Register. The suspended program or erase cycle can be resumed by mean of the
Program/Erase Resume instruction (PER). During the program/erase cycles also the polling
instructions (to check if the internal modify cycle is finished by mean of the WIP bit of the
Status Register or of the Program/Erase controller bit of the Flag Status register) are also
accepted to allow the application checking the end of the internal modify cycles, of course
these polling instructions don't affect the internal cycles performing.
High Impedance
0
1
2
Instruction
3
4
5
6
7
Deep power-down mode
t
RDP
Standby mode
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