N25Q128A11B1240E NUMONYX, N25Q128A11B1240E Datasheet - Page 132
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N25Q128A11B1240E
Manufacturer Part Number
N25Q128A11B1240E
Description
Manufacturer
NUMONYX
Datasheet
1.N25Q128A11B1240E.pdf
(185 pages)
Specifications of N25Q128A11B1240E
Cell Type
NOR
Density
128Mb
Access Time (max)
7ns
Interface Type
Serial (SPI)
Boot Type
Bottom
Address Bus
1b
Operating Supply Voltage (typ)
1.8V
Operating Temp Range
-40C to 85C
Package Type
TBGA
Program/erase Volt (typ)
1.7 to 2/8.5 to 9.5V
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
1.7V
Operating Supply Voltage (max)
2V
Word Size
8b
Number Of Words
16M
Supply Current
20mA
Mounting
Surface Mount
Pin Count
24
Lead Free Status / Rohs Status
Supplier Unconfirmed
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9.3
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S
C
DQ0
DQ1
Release from Deep Power-down (RDP)
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down (RDP) instruction. Executing this instruction
takes the device out of the Deep Power-down mode.
Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Release from Deep-Power-down (RDP)
instruction of the Extended SPI protocol. The instruction sequence is shown in
Release from Deep Power-down instruction
Figure 71. Release from Deep Power-down instruction sequence
QIO-SPI Instructions
In QIO-SPI protocol, instructions, addresses and Input/Output data always run in parallel on
four wires: DQ0, DQ1, DQ2 and DQ3 with the already mentioned exception of the modify
instruction (erase and program) performed with the VPP=VPPh.
In the case of a Quad Command Fast Read (QCFR), Read OTP (ROTP), Read Lock
Registers (RDLR), Read Status Register (RDSR), Read Flag Status Register (RFSR), Read
NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR),
Read Volatile Enhanced Configuration Register (RDVECR) and Read Identification (RDID)
instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip
Select (S) can be driven High after any bit of the data-out sequence is being shifted out.
In the case of a Quad Command Page Program (QCPP), Program OTP (POTP), Subsector
Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Program/Erase Suspend (PES),
Program/Erase Resume (PER), Write Status Register (WRSR), Clear Flag Status Register
(CLFSR), Write to Lock Register (WRLR), Write Configuration Register (WRVCR), Write
Enhanced Configuration Register (WRVECR), Write NV Configuration Register (WRNVCR),
Write Enable (WREN) or Write Disable (WRDI) instruction, Chip Select (S) must be driven
High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed.
0
Instruction
1
2
3
High Impedance
Deep power-down mode
t
RDP
sequence.
Standby mode
Figure 71:
Dual_RDP
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