N25Q128A11B1240E NUMONYX, N25Q128A11B1240E Datasheet - Page 48

• Manufacturer Part Number: N25Q128A11B1240E
• Manufacturer: NUMONYX

Specifications of N25Q128A11B1240E

• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 7ns
• Interface Type: Serial (SPI)
• Boot Type: Bottom
• Address Bus: 1b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: TBGA
• Program/erase Volt (typ): 1.7 to 2/8.5 to 9.5V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 8b
• Number Of Words: 16M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / Rohs Status: Supplier Unconfirmed

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Protection modes
There are protocol-related and specific hardware and software protection modes. They are
described below.
SPI Protocol-related protections
This applies to all three protocols. The environments where non-volatile memory devices
are used can be very noisy. No SPI device can operate correctly in the presence of
excessive noise. To help combat this, the N25Q128 features the following data protection
mechanisms:
This bit is also returned to its reset state after all the analogous events in DIO-SPI and QIO-
SPI protocol modes.
Specific hardware and software protection
There are two software protected modes, SPM1 and SPM2, that can be combined to protect
the memory array as required. The SPM2 can be locked by hardware with the help of the W
input pin.
SPM1
The first software protected mode (SPM1) is managed by specific Lock Registers assigned
to each 64 Kbyte sector.
Power On Reset and an internal timer (tPUW) can provide protection against
inadvertent changes while the power supply is outside the operating specification.
Program, Erase, and Write Status Register instructions are checked to ensure the
instruction includes a number of clock pulses that is a multiple of a byte before they are
accepted for execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events (in Extended SPI protocol mode):
–
–
–
–
–
–
–
–
–
–
–
–
–
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write to Lock Register (WRLR) instruction completion
Program OTP (POTP) instruction completion
Page Program (PP) instruction completion
Dual Input Fast Program (DIFP) instruction completion
Dual Input Extended Fast Program (DIEFP) instruction completion
Quad Input Fast Program (QIFP) instruction completion
Quad Input Extended Fast Program (QIEFP) instruction completion
Subsector Erase (SSE) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion