MT29F1G08ABADAWP-IT:D Micron Technology Inc, MT29F1G08ABADAWP-IT:D Datasheet

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MT29F1G08ABADAWP-IT:D

Manufacturer Part Number
MT29F1G08ABADAWP-IT:D
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT29F1G08ABADAWP-IT:D

Lead Free Status / Rohs Status
Compliant
NAND Flash Memory
MT29F1G08ABADAWP, MT29F1G08ABBDAH4,
MT29F1G08ABBDAHC, MT29F1G16ABBDAH4,
MT29F1G16ABBDAHC, MT29F1G08ABADAH4
Features
PDF: 09005aef83e5ffed
m68a.pdf – Rev. D 06/10 EN
• Open NAND Flash Interface (ONFI) 1.0-compliant
• Single-level cell (SLC) technology
• Organization
• Asynchronous I/O performance
• Array performance
• Command set: ONFI NAND Flash Protocol
• Advanced command set
• Operation status byte provides software method for
• Internal data move operations supported within the
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
– Page size x8: 2112 bytes (2048 + 64 bytes)
– Page size x16: 1056 words (1024 + 32 words)
– Block size: 64 pages (128K + 4K bytes)
– Device size: 1Gb: 1024 blocks
– Read page: 25µs
– Program page: 200µs (TYP, 3.3V and 1.8V)
– Erase block: 700µs (TYP)
– Program page cache mode
– Read page cache mode
– One-time programmable (OTP) mode
– Read unique ID
– Internal data move
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
device from which data is read
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
t
RC/
t
WC: 20ns (3.3V), 25ns (1.8V)
3
5
5
Micron Confidential and Proprietary
3
1
1
• Ready/busy# (R/B#) signal provides a hardware
• WP# signal: write protect entire device
• First block (block address 00h) is valid when ship-
• Block 0 requires 1-bit ECC if PROGRAM/ERASE cy-
• RESET (FFh) required as first command after power-
• Alternate method of device initialization (Nand_In-
• Quality and reliability
• Operating Voltage Range
• Operating temperature:
• Package
Notes:
method for detecting operation completion
ped from factory with ECC. For minimum required
ECC, see Error Management.
cles are less than 1000
on
it) after power up
– Data retention: 10 years
– V
– V
– Commercial: 0°C to +70°C
– Extended (ET): –40ºC to +85ºC
– 48-pin TSOP type 1, CPL
– 63-ball VFBGA
Micron Technology, Inc. reserves the right to change products or specifications without notice.
CC
CC
1Gb x8, x16: NAND Flash Memory
: 2.7–3.6V
: 1.7–1.95V
1. The ONFI 1.0 specification is available at
2. CPL = Center parting line.
3. See Electrical Specifications for
4. Available only in the 1.8V VFBGA package.
5. Supported only with ECC disabled.
www.onfi.org.
t
PROG_ECC specifications.
4
(contact factory)
© 2010 Micron Technology, Inc. All rights reserved.
2
Preliminary
t
Features
R_ECC and

MT29F1G08ABADAWP-IT:D Summary of contents

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... NAND Flash Memory MT29F1G08ABADAWP, MT29F1G08ABBDAH4, MT29F1G08ABBDAHC, MT29F1G16ABBDAH4, MT29F1G16ABBDAHC, MT29F1G08ABADAH4 Features • Open NAND Flash Interface (ONFI) 1.0-compliant • Single-level cell (SLC) technology • Organization – Page size x8: 2112 bytes (2048 + 64 bytes) – Page size x16: 1056 words (1024 + 32 words) – Block size: 64 pages (128K + 4K bytes) – ...

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Part Numbering Information Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type, visit www.micron.com/products. Contact the factory for ...

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Contents General Description ......................................................................................................................................... 8 Signal Descriptions and Assignments ................................................................................................................ 8 Signal Assignments ........................................................................................................................................... 8 Package Dimensions ...................................................................................................................................... 12 Architecture ................................................................................................................................................... 15 Device and Array Organization ....................................................................................................................... 16 Asynchronous Interface Bus Operation ........................................................................................................... 18 Asynchronous Enable/Standby ................................................................................................................... 18 Asynchronous Commands ...

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OTP DATA PROTECT (80h-10) .................................................................................................................... 67 OTP DATA READ (00h-30h) ........................................................................................................................ 69 Error Management ......................................................................................................................................... 71 Internal ECC and Spare Area Mapping for ECC ................................................................................................ 73 Electrical Specifications .................................................................................................................................. 75 Electrical Specifications – AC Characteristics and Operating Conditions ........................................................... 77 ...

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List of Tables Table 1: Asynchronous Signal Definitions ........................................................................................................ 8 Table 2: Array Addressing (x8) ........................................................................................................................ 16 Table 3: Array Addressing (x16) ...................................................................................................................... 17 Table 4: Asynchronous Interface Mode Selection ........................................................................................... 18 Table 5: Command Set .................................................................................................................................. 29 Table 6: ...

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List of Figures Figure 1: Marketing Part Number Chart .......................................................................................................... 2 Figure 2: 48-Pin TSOP – Type 1, CPL (Top View) ............................................................................................... 8 Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View) ....................................................................................... 10 Figure 4: 63-Ball VFBGA, x16 (Balls ...

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Figure 50: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Operation Mode) ........................................................................................................................................................ 67 Figure 51: OTP DATA PROTECT Operation (After Entering OTP Protect Mode) ................................................ 68 Figure 52: OTP DATA READ .......................................................................................................................... 69 Figure 53: OTP ...

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General Description Micron NAND Flash devices include an asynchronous data interface for high-perform- ance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer commands, address, and data. There are five control signals used to implement the ...

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R/B# R/B# RE# RE# CE# CE Vcc Vcc Vss Vss CLE CLE ALE ALE WE# WE# WP# WP# ...

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Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View These pins might not be bonded inthe package; however, Micron recommends that the ...

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Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory ...

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Package Dimensions Figure 5: 48-Pin TSOP – Type 1, CPL 1 12.00 ±0.08 24 +0.03 0.15 -0.02 1. All dimensions are in millimeters. Note: PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory 20.00 ±0.25 ...

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Figure 6: 63-Ball VFBGA (HC) Seating plane A 0.12 A 63X Ø0.45 Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). Dimensions apply solder balls post- reflow on Ø0.4 SMD ball pads. 8.8 CTR 0.8 TYP ...

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Figure 7: 63-Ball VFBGA (H4) 9mm x 11mm Seating plane A 0.12 A 63X Ø0.45 Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). Dimensions apply to solder balls post reflow on Ø0.4 SMD ball pads. ...

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Architecture These devices use NAND Flash electrical and command interfaces. Data, commands, and addresses are multiplexed onto the same pins and received by I/O control circuits. The commands received at the I/O control circuits are latched by a command register ...

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Device and Array Organization Figure 9: Array Organization – x8 Cache Register Data Register 1024 blocks per device Table 2: Array Addressing (x8) Cycle I/O7 I/O6 First CA7 CA6 Second LOW LOW Third BA7 BA6 Fourth BA15 BA14 1. If ...

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Figure 10: Array Organization – x16 Cache Register Data Register 1024 blocks per device Table 3: Array Addressing (x16) Cycle I/O[15:8] I/O7 First LOW CA7 Second LOW LOW Third LOW BA7 Fourth LOW BA15 1. If CA10 is 1, then ...

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Asynchronous Interface Bus Operation The bus on the device is multiplexed. Data I/O, addresses, and commands all share the same pins. I/O[15:8] are used only for data in the x16 configuration. Addresses and com- mands are always supplied on I/O[7:0]. ...

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Figure 11: Asynchronous Command Latch Cycle CLE CE# WE# ALE I/Ox PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Asynchronous Interface Bus Operation t t CLS CLH ...

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Asynchronous Addresses An asynchronous address is written from I/O[7:0] to the address register on the rising edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH. Bits that are not part of the ...

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Asynchronous Data Input Data is written to the cache register of the selected die (LUN) on the rising edge of WE# when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH. Data input is ignored by ...

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Asynchronous Data Output Data can be output from a die (LUN READY state. Data output is supported following a READ operation from the NAND Flash array. Data is output from the cache register of the ...

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Figure 15: Asynchronous Data Output Cycles (EDO Mode) CE# RE# t CEA I/ RDY Write Protect# The write protect# (WP#) signal enables or disables PROGRAM and ERASE operations to a target. When WP# is LOW, PROGRAM and ERASE ...

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R/B# outputs to be OR-tied. Typically, R/B# is connected to an interrupt pin on the system controller. The combination of Rp and capacitive loading of the R/B# circuit determines the rise time of the R/B# signal. The ...

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Figure 17: Fall and Rise (3.3V V 3.50 3.00 2.50 2.00 V 1.50 1.00 0.50 0. Fall and Notes Rise dependent on external capacitance and resistive loading and output transistor im- pedance ...

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Figure 19 (mA) Figure 20: I vs. Rp (1. (mA) PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN Asynchronous Interface Bus Operation ) CC 3.50 3.00 ...

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Figure 21: TC vs. Rp T(ns) PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN Asynchronous Interface Bus Operation 1200 1000 800 600 400 200 0 0 2000 4000 27 Micron Technology, Inc. reserves the right to change products or specifications ...

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Device Initialization Micron NAND Flash devices are designed to prevent data corruption during power tran- sitions. V protection during power transitions.) When ramping V to initialize the device: 1. Ramp V 2. The host must wait for R/ ...

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Command Definitions Table 5: Command Set Command Command Cycle #1 Reset Operations RESET Identification Operation READ ID READ PARAMETER PAGE READ UNIQUE ID Feature Operations GET FEATURES SET FEATURES Status Operations READ STATUS Column Address Operations RANDOM DATA READ RANDOM ...

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Table 5: Command Set (Continued) Command Command Cycle #1 OTP DATA LOCK BY BLOCK (ONFI) OTP DATA PROGRAM (ONFI) OTP DATA READ (ONFI) 1. Busy means RDY = 0. Notes not cross plane address boundaries when using READ ...

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Reset Operations RESET (FFh) The RESET command is used to put the memory device into a known condition and to abort the command sequence in progress. READ, PROGRAM, and ERASE commands can be aborted while the device is in the ...

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Identification Operations READ ID (90h) The READ ID (90h) command is used to read identifier codes programmed into the tar- get. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing 90h ...

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READ ID Parameter Tables Table 6: READ ID Parameters for Address 00h b = binary hexadecimal Options Byte 0 – Manufacturer ID Manufacturer Micron Byte 1 – Device ID MT29F1G08ABADA 1Gb, x8, 3.3V MT29F1G08ABBDA 1Gb, x8, 1.8V MT29F1G16ABBDA ...

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Table 6: READ ID Parameters for Address 00h (Continued binary hexadecimal Options Byte value MT29F1G08ABADA MT29F1G08ABBDA MT29F1G16ABBDA Table 7: READ ID Parameters for Address 20h h = hexadecimal Byte Options I/07 “O” “N” 1 ...

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READ PARAMETER PAGE (ECh) The READ PARAMETER PAGE (ECh) command is used to read the ONFI parameter page programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing ...

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... MT29F1G08ABADAWP 4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 30h, 38h, 41h, 42h, 41h, 44h, 41h, 33h, 50h, 20h, 20h, 20h, 20h ...

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... MT29F1G08ABADA3W 3Fh, 00h MT29F1G08ABBDA3W 1Fh, 00h MT29F1G16ABBDA3W 1Fh, 00h MT29F1G08ABADAWP 3Fh, 00h MT29F1G08ABBDAHC 1Fh, 00h MT29F1G16ABBDAHC 1Fh, 00h MT29F1G08ABBDAH4 1Fh, 00h MT29F1G16ABBDAH4 1Fh, 00h MT29F1G08ABADAH4 ...

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... PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Parameter Page Data Structure Tables Value MT29F1G08ABADA3W 3Fh, 00h MT29F1G08ABBDA3W 1Fh, 00h MT29F1G16ABBDA3W 1Fh, 00h MT29F1G08ABADAWP 3Fh, 00h MT29F1G08ABBDAHC 1Fh, 00h MT29F1G16ABBDAHC 1Fh, 00h MT29F1G08ABBDAH4 1Fh, 00h MT29F1G16ABBDAH4 1Fh, 00h MT29F1G08ABADAH4 ...

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READ UNIQUE ID (EDh) The READ UNIQUE ID (EDh) command is used to read a unique identifier programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing EDh ...

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Feature Operations The SET FEATURES (EFh) and GET FEATURES (EEh) commands are used to modify the target's default power-on behavior. These commands use a one-byte feature address to determine which subfeature parameters will be read or modified. Each feature address ...

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Table 10: Feature Address 90h – Array Operation Mode Subfeature Parameter Options 1/O7 P1 Operation Normal mode option OTP operation OTP protection Disable ECC Enable ECC P2 Reserved P3 Reserved P4 Reserved Note: 1. These bits are reset to 00h ...

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GET FEATURES (EEh) The GET FEATURES (EEh) command reads the subfeature parameters (P1–P4) from the specified feature address. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing EEh to the command ...

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Table 11: Feature Addresses 01h: Timing Mode Subfeature Parameter Options P1 Timing mode Mode 0 (default) Mode 1 Mode 2 Mode 3 Mode 4 Mode The timing mode feature address is used to change the ...

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Table 12: Feature Addresses 80h: Programmable I/O Drive Strength Subfeature Parameter Options P1 I/O drive strength Full (default) Three-quarters One-half One-quarter The programmable drive strength feature address is used to change the default I/O Note: drive ...

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Status Operations Each die (LUN) provides its status independently of other die (LUNs) on the same tar- get through its 8-bit status register. After the READ STATUS (70h) command is issued, status register output is enabled. The contents of the ...

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READ STATUS (70h) The READ STATUS (70h) command returns the status of the last-selected die (LUN target. This command is accepted by the last-selected die (LUN) even when it is busy (RDY = 0). If there is only ...

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Column Address Operations The column address operations affect how data is input to and output from the cache registers within the selected die (LUNs). These features provide host flexibility for man- aging data, especially when the host internal buffer is ...

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RANDOM DATA INPUT (85h) The RANDOM DATA INPUT (85h) command changes the column address of the selec- ted cache register and enables data input on the last-selected die (LUN). This command is accepted by the selected die (LUN) when it ...

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PROGRAM PAGE CACHE (80h-15h), and PROGRAM FOR INTERNAL DATA MOVE (85h-10h). When used with these commands, the LUN address and plane select bits are required to be identical to the LUN address and plane select bits originally specified. The PROGRAM ...

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Read Operations The READ PAGE (00h-30h) command, when issued by itself, reads one page from the NAND Flash array to its cache register and enables data output for that cache register. During data output the following commands can be used ...

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READ MODE (00h) The READ MODE (00h) command disables status output and enables data output for the last-selected die (LUN) and cache register after a READ operation (00h-30h, 00h-3Ah, 00h-35h) has been monitored with a status operation (70h). This command ...

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Figure 34: READ PAGE (00h-30h) Operation Cycle type Command Address I/O[7:0] 00h C1 RDY Figure 35: READ PAGE (00h-30h) Operation with Internal ECC Enabled RDY I/O[7:0] 00h Address Address READ PAGE CACHE SEQUENTIAL (31h) The READ PAGE CACHE SEQUENTIAL (31h) ...

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Figure 36: READ PAGE CACHE SEQUENTIAL (31h) Operation Cycle type Command Address x4 Command I/O[7:0] 00h Page Address M 30h t WB RDY READ PAGE CACHE RANDOM (00h-31h) The READ PAGE CACHE RANDOM (00h-31h) command reads the specified block and ...

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Figure 37: READ PAGE CACHE RANDOM (00h-31h) Operation Cycle type Command Address x4 Command 00h Page Address M 30h I/O[7:0] RDY Cycle type D Command Address x4 OUT I/O[7:0] 00h Page Address P Dn RDY 1 PDF: 09005aef83e5ffed m68a.pdf – ...

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READ PAGE CACHE LAST (3Fh) The READ PAGE CACHE LAST (3Fh) command ends the read page cache sequence and copies a page from the data register to the cache register. This command is accepted by the die (LUN) when it ...

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Program Operations Program operations are used to move data from the cache or data registers to the NAND array. During a program operation the contents of the cache and/or data regis- ters are modified by the internal control logic. Within ...

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When internal ECC is enabled, the duration of array programming time is During plete. Figure 39: PROGRAM PAGE (80h-10h) Operaton Cycle type Command Address Address I/O[7:0] 80h C1 C2 RDY PROGRAM PAGE CACHE (80h-15h) The PROGRAM PAGE CACHE (80h-15h) command ...

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Figure 40: PROGRAM PAGE CACHE (80h-15h) Operation (Start) Cycle type Command Address Address I/O[7:0] 80h C1 C2 RDY Cycle type Command Address Address I/O[7:0] 80h C1 C2 RDY 1 Figure 41: PROGRAM PAGE CACHE (80h-15h) Operation (End) As defined for ...

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Erase Operations Erase operations are used to clear the contents of a block in the NAND Flash array to prepare its pages for program operations. Erase Operations The ERASE BLOCK (60h-D0h) command erases one block in the NAND Flash array. ...

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Internal Data Move Operations Internal data move operations make it possible to transfer data within a device from one page to another using the cache register. This is particularly useful for block man- agement and wear leveling. The INTERNAL DATA ...

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Figure 43: READ FOR INTERNAL DATA MOVE (00h-35h) Operation Cycle type Command Address I/O[7:0] 00h RDY Figure 44: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h) Cycle type Command Address I/O[7:0] 00h C1 RDY Cycle type Command ...

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Figure 45: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled t R_ECC R/B# Address I/O[7:0] 00h 35h (4 cycles) Source address Figure 46: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled t R_ECC R/B# Address I/O[7:0] ...

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PROGRAM FOR INTERNAL DATA MOVE (85h–10h) The PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command is functionally iden- tical to the PROGRAM PAGE (80h-10h) command, except that when 85h is written to the command register, cache register contents are not cleared. ...

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One-Time Programmable (OTP) Operations This Micron NAND Flash device offers a protected, one-time programmable NAND Flash memory area. Thirty full pages (2112 bytes per page) of OTP data are available on the device, and the entire range is guaranteed to ...

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OTP DATA PROGRAM (80h-10h) The OTP DATA PROGRAM (80h-10h) command is used to write data to the pages within the OTP area. An entire page can be programmed at one time page can be partially programmed up to ...

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RANDOM DATA INPUT (85h) After the initial OTP data set is input, additional data can be written to a new column address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT command can be used any number of ...

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Figure 50: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Opera- tion Mode) CLE CE WE# ALE RE# Col Col OTP I/Ox 80h 1 page add1 add2 SERIAL DATA INPUT command R/B# 1. The OTP ...

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Figure 51: OTP DATA PROTECT Operation (After Entering OTP Protect Mode) CLE CE WE# ALE RE# Col I/Ox 80h 00h OTP DATA PROTECT command R/B# 1. OTP data is protected following a good status confirmation. Note: PDF: 09005aef83e5ffed ...

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OTP DATA READ (00h-30h) To read data from the OTP area, set the device to OTP operation mode, then issue the PAGE READ (00h-30h) command. Data can be read from OTP pages within the OTP area whether the area is ...

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Figure 53: OTP DATA READ with RANDOM DATA READ Operation CLE CE# WE# ALE RE# Col Col OTP I/Ox 00h add 1 add 2 page Column address n R/B# Note: 1. The OTP page must be within the range 02h–1Fh. ...

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Error Management Each NAND Flash die (LUN) is specified to have a minimum number of valid blocks (NVB) of the total available blocks. This means the die (LUNs) could have blocks that are invalid when shipped from the factory. An ...

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Table 15: Error Management Details (Continued) Description Minimum required ECC for block 0 if PROGRAM/ ERASE cycles are less than 1000 PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Error Management Requirement 1-bit ECC ...

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Internal ECC and Spare Area Mapping for ECC Internal ECC enables 5-bit detection and 4-bit error correction in 512 bytes (x8) or 256 words (x16) of the main area and 4 bytes (x8 words (x16) of metadata I ...

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Figure 55: Spare Area Mapping (x16) Max word Min word ECC Protected Address Address 0FFh 000h Yes 1FFh 100h Yes 2FFh 200h Yes 3FFh 300h Yes 400h 400h No 401h 401h No 403h 402h Yes 407h 404h Yes 408h 408h ...

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Electrical Specifications Stresses greater than those listed can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections ...

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Table 19: Capacitance Description Input capacitance Input/output capacitance (I/O) 1. These parameters are verified in device characterization and are not 100% tested. Notes: 2. Test conditions: T Table 20: Test Conditions Parameter Input pulse levels Input rise and fall times ...

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Electrical Specifications – AC Characteristics and Operating Conditions Table 21: AC Characteristics: Command, Data, and Address Input (3.3V) Note 1 applies to all Parameter ALE to data start ALE hold time ALE setup time CE# hold time CLE hold time ...

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Table 23: AC Characteristics: Normal Operation (3.3V) Note 1 applies to all Parameter ALE to RE# delay CE# access time CE# HIGH to output High-Z CLE to RE# delay CE# HIGH to output hold Output High-Z to RE# LOW READ ...

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Table 24: AC Characteristics: Normal Operation (1.8V) (Continued) Note 1 applies to all Parameter RE# HIGH to output High-Z RE# LOW to output hold RE# pulse width Ready to RE# LOW Reset time (READ/PROGRAM/ERASE) WE# HIGH to busy WE# HIGH ...

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Electrical Specifications – DC Characteristics and Operating Conditions Table 25: DC Characteristics and Operating Conditions (3.3V) Parameter Conditions t t Sequential READ current (MIN); CE PROGRAM current ERASE current Standby current (TTL) WP# = 0V/V ...

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Table 26: DC Characteristics and Operating Conditions (1.8V) Parameter Conditions t t Sequential READ current (MIN); CE PROGRAM current ERASE current Standby current (TTL) WP# = 0V/V Standby current (CMOS) CE WP# = ...

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Electrical Specifications – Program/Erase Characteristics Table 27: ProgramErase Characteristics Parameter Number of partial-page programs BLOCK ERASE operation time Busy time for PROGRAM CACHE operation Cache read busy time Busy time for SET FEATURES and GET FEATURES operations Busy time for ...

Page 83

Asynchronous Interface Timing Diagrams Figure 56: RESET Operation CLE CE WE# R/B# FFh I/O[7:0] RESET command Figure 57: READ STATUS Cycle CLE CE# WE# RE# I/O[7:0] PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND ...

Page 84

Figure 58: READ PARAMETER PAGE CLE WE ALE RE# I/O[7:0] ECh 00h R/B# Figure 59: READ PAGE CLE CE WE# ALE RE# Col I/Ox 00h add 1 add 2 RDY PDF: 09005aef83e5ffed m68a.pdf – Rev. D ...

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Figure 60: READ PAGE Operation with CE# “Don’t Care” CLE CE# RE# ALE RDY WE# I/Ox 00h Address (4 cycles) PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Asynchronous Interface Timing Diagrams t t ...

Page 86

Figure 61: RANDOM DATA READ CLE CE# WE# ALE t RC RE# D I/Ox OUT RDY PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Asynchronous Interface Timing Diagrams t RHW Col ...

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Figure 62: READ PAGE CACHE SEQUENTIAL CLE t CLS t CLH CE WE# ALE RE Col Col I/Ox 00h add 1 add 2 Column address 00h RDY CLE t CLS ...

Page 88

Figure 63: READ PAGE CACHE RANDOM CLE t CLS t CLH CE WE# ALE RE Col I/Ox 00h add 1 Column address 00h RDY CLE CE# WE# ALE RE# t ...

Page 89

Figure 64: READ ID Operation CLE CE# WE# ALE RE# I/Ox 90h 00h or 20h Address, 1 cycle Figure 65: PROGRAM PAGE Operation CLE CE WE# ALE RE# Col Col I/Ox 80h add 1 add 2 RDY PDF: ...

Page 90

Figure 66: PROGRAM PAGE Operation with CE# “Don’t Care” CLE CE# WE# ALE I/Ox 80h Address (4 cycles) Figure 67: PROGRAM PAGE Operation with RANDOM DATA INPUT CLE CE WE# ALE RE# Col Col Row Row i/Ox 80h ...

Page 91

Figure 68: PROGRAM PAGE CACHE CLE CE WE# ALE RE# Row Row D Col Col I/Ox 80h IN add 1 add 2 add 1 add 2 N Serial input RDY Last page - 1 Figure 69: PROGRAM PAGE ...

Page 92

Figure 70: INTERNAL DATA MOVE CLE CE WE# ALE RE# Col Col Row Row I/Ox 00h add 1 add 2 add 1 add 2 RDY Figure 71: ERASE BLOCK Operation CLE CE WE# ALE RE# Row ...

Page 93

Revision History Rev. D, Preliminary – 6/10 • Added block endurance info back in to Parameter Page Data Structure Table Rev C, Preliminary – 4/10 • Added part numbers to document • Removed Endurance spec from Features and Parameter Page ...

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