MT29F1G08ABADAWP-IT:D Micron Technology Inc, MT29F1G08ABADAWP-IT:D Datasheet - Page 15

• Manufacturer Part Number: MT29F1G08ABADAWP-IT:D
• Manufacturer: Micron Technology Inc

Specifications of MT29F1G08ABADAWP-IT:D

• Lead Free Status / Rohs Status: Compliant

Architecture
Figure 8: NAND Flash Die (LUN) Functional Block Diagram
PDF: 09005aef83e5ffed
m68a.pdf – Rev. D 06/10 EN
WE#
WP#
R/B#
I/Ox
ALE
CE#
RE#
CLE
control
Control
logic
I/O
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins and received by I/O control circuits.
The commands received at the I/O control circuits are latched by a command register
and are transferred to control logic circuits for generating internal signals to control de-
vice operations. The addresses are latched by an address register and sent to a row
decoder to select a row address, or to a column decoder to select a column address.
Data is transferred to or from the NAND Flash memory array, byte by byte (x8) or word
by word (x16), through a data register and a cache register.
The NAND Flash memory array is programmed and read using page-based operations
and is erased using block-based operations. During normal page operations, the data
and cache registers act as a single register. During cache operations, the data and cache
registers operate independently to increase data throughput. The status register reports
the status of die operations.
Command register
Address register
Status register
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb x8, x16: NAND Flash Memory
Column decode
Cache register
NAND Flash
Data register
(2 planes)
array
ECC
© 2010 Micron Technology, Inc. All rights reserved.
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CC
Architecture
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SS