MT29F1G08ABADAWP-IT:D Micron Technology Inc, MT29F1G08ABADAWP-IT:D Datasheet - Page 17

• Manufacturer Part Number: MT29F1G08ABADAWP-IT:D
• Manufacturer: Micron Technology Inc

Specifications of MT29F1G08ABADAWP-IT:D

• Lead Free Status / Rohs Status: Compliant

Figure 10: Array Organization – x16
Table 3: Array Addressing (x16)
PDF: 09005aef83e5ffed
m68a.pdf – Rev. D 06/10 EN
Cycle
First
Second
Third
Fourth
Cache Register
Data Register
I/O[15:8]
1024 blocks
per device
LOW
LOW
LOW
LOW
Notes:
BA15
LOW
I/O7
CA7
BA7
1. If CA10 is 1, then CA[9:5] must be 0.
2. Block address concatenated with page address = actual page address. CAx = column ad-
3. I/O[15:8] are not used during the addressing sequence and should be driven LOW.
dress; PAx = page address; BAx = block address.
BA14
LOW
I/O6
CA6
BA6
1024
1024
1 block
1056 words
BA13
LOW
I/O5
CA5
PA5
17
32
32
BA12
LOW
I/O4
CA4
PA4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb x8, x16: NAND Flash Memory
64 pages = 1 block
1 page
1 block
1 device = (1K + 32) words x 64 pages
BA11
Device and Array Organization
LOW
I/O3
CA3
PA3
I/O15
I/O0
= (1K + 32) words
= (1K + 32) words x 64 pages
= (64K + 2K) words
= 1056Mb
x 1024 blocks
(64K + 2K) words
CA10
BA10
I/O2
CA2
PA2
1
© 2010 Micron Technology, Inc. All rights reserved.
I/O1
CA1
CA9
BA9
PA1
I/O0
CA0
CA8
BA8
PA0