MT29F1G08ABADAWP-IT:D Micron Technology Inc, MT29F1G08ABADAWP-IT:D Datasheet - Page 57

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MT29F1G08ABADAWP-IT:D

Manufacturer Part Number
MT29F1G08ABADAWP-IT:D
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT29F1G08ABADAWP-IT:D

Lead Free Status / Rohs Status
Compliant

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0
Figure 39: PROGRAM PAGE (80h-10h) Operaton
PROGRAM PAGE CACHE (80h-15h)
PDF: 09005aef83e5ffed
m68a.pdf – Rev. D 06/10 EN
Cycle type
I/O[7:0]
RDY
Command
80h
Address
C1
When internal ECC is enabled, the duration of array programming time is
During
plete.
The PROGRAM PAGE CACHE (80h-15h) command enables the host to input data to a
cache register; copies the data from the cache register to the data register; then moves
the data register contents to the specified block and page address in the array of the
selected die (LUN). After the data is copied to the data register, the cache register is avail-
able for additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h)
commands. The PROGRAM PAGE CACHE (80h-15h) command is accepted by the die
(LUN) when it is ready (RDY =1, ARDY = 1). It is also accepted by the die (LUN) when
busy with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
To input a page to the cache register to move it to the NAND array at the block and page
address specified, write 80h to the command register. Issuing the 80h to the command
register clears all of the cache registers' contents on the selected target. Then write n
address cycles containing the column address and row address. Data input cycles fol-
low. Serial data is input beginning at the column address specified. At any time during
the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM FOR INTERNAL
DATA INPUT (85h) commands may be issued. When data input is complete, write 15h
to the command register. The selected LUN will go busy
(RDY = 0, ARDY = 0) for
previous program cache operation, to copy data from the cache register to the data reg-
ister, and then to begin moving the data register contents to the specified page and
block address.
To determine the progress of
alternatively, the status operation (70h) can be used. When the LUN’s status shows that
it is busy with a PROGRAM CACHE operation (RDY = 1, ARDY = 0), the host should
check the status of the FAILC bit to see if a previous cache operation was successful.
If, after
out issuing the PROGRAM PAGE (80h-10h) command, the host should monitor ARDY
until it is 1. The host should then check the status of the FAIL and FAILC bits.
Address
C2
t
t
PROG_ECC, the internal ECC generates parity bits when error detection is com-
CBSY, the host wants to wait for the program cache operation to complete, with-
Address
R1
Address
R2
t
t
ADL
CBSY to allow the data register to become available from a
57
t
D
D0
CBSY, the host can monitor the target's R/B# signal or,
IN
D
D1
IN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb x8, x16: NAND Flash Memory
D
IN
D
Dn
IN
Command
10h
Program Operations
t
WB
© 2010 Micron Technology, Inc. All rights reserved.
t
t
PROG_ECC
PROG or
Command
t
70h
PROG_ECC.
Status
D
OUT

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