MT29F1G08ABADAWP-IT:D Micron Technology Inc, MT29F1G08ABADAWP-IT:D Datasheet - Page 48

• Manufacturer Part Number: MT29F1G08ABADAWP-IT:D
• Manufacturer: Micron Technology Inc

Specifications of MT29F1G08ABADAWP-IT:D

• Lead Free Status / Rohs Status: Compliant

RANDOM DATA INPUT (85h)
Figure 32: RANDOM DATA INPUT (85h) Operation
PROGRAM FOR INTERNAL DATA INPUT (85h)
PDF: 09005aef83e5ffed
m68a.pdf – Rev. D 06/10 EN
Cycle type
I/O[7:0]
RDY
As defined for PAGE
(CACHE) PROGRAM
D
The RANDOM DATA INPUT (85h) command changes the column address of the selec-
ted cache register and enables data input on the last-selected die (LUN). This command
is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also
accepted by the selected die (LUN) during cache program operations
(RDY = 1; ARDY = 0).
Writing 85h to the command register, followed by two column address cycles contain-
ing the column address, puts the selected die (LUN) into data input mode. After the
second address cycle is issued, the host must wait at least
The selected die (LUN) stays in data input mode until another valid command is issued.
Though data input mode is enabled, data input from the host is optional. Data input
begins at the column address specified.
The RANDOM DATA INPUT (85h) command is allowed after the required address cy-
cles are specified, but prior to the final command cycle (10h, 11h, 15h) of the following
commands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM PAGE
CACHE (80h-15h),and PROGRAM FOR INTERNAL DATA MOVE (85h-10h).
Dn
The PROGRAM FOR INTERNAL DATA INPUT (85h) command changes the row address
(block and page) where the cache register contents will be programmed in the NAND
Flash array. It also changes the column address of the selected cache register and ena-
bles data input on the specified die (LUN). This command is accepted by the selected
die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die
(LUN) during cache programming operations (RDY = 1; ARDY = 0).
Write 85h to the command register. Then write two column address cycles and three
row address cycles. This updates the page and block destination of the selected device
for the addressed LUN and puts the cache register into data input mode. After the fifth
address cycle is issued the host must wait at least
ted LUN stays in data input mode until another valid command is issued. Though data
input mode is enabled, data input from the host is optional. Data input begins at the
column address specified.
The PROGRAM FOR INTERNAL DATA INPUT (85h) command is allowed after the re-
quired address cycles are specified, but prior to the final command cycle (10h, 11h, 15h)
of the following commands while data input is permitted: PROGRAM PAGE (80h-10h),
IN
Dn + 1
D
IN
Command
85h
Address
C1
48
Address
C2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb x8, x16: NAND Flash Memory
t
ADL
Column Address Operations
t
ADL before inputting data. The selec-
D
Dk
IN
As defined for PAGE
(CACHE) PROGRAM
t
Dk + 1
ADL before inputting data.
D
IN
© 2010 Micron Technology, Inc. All rights reserved.
Dk + 2
D
IN