MT29F1G08ABADAWP-IT:D Micron Technology Inc, MT29F1G08ABADAWP-IT:D Datasheet - Page 16

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MT29F1G08ABADAWP-IT:D

Manufacturer Part Number
MT29F1G08ABADAWP-IT:D
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT29F1G08ABADAWP-IT:D

Lead Free Status / Rohs Status
Compliant

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0
Device and Array Organization
Figure 9: Array Organization – x8
Table 2: Array Addressing (x8)
PDF: 09005aef83e5ffed
m68a.pdf – Rev. D 06/10 EN
Cycle
First
Second
Third
Fourth
Cache Register
Data Register
1024 blocks
per device
BA15
LOW
I/O7
CA7
BA7
Notes:
1. If CA11 is 1, then CA[10:6] must be 0.
2. Block address concatenated with page address = actual page address; CAx = column ad-
BA14
LOW
I/O6
CA6
BA6
dress; PAx = page address; BAx = block address.
2048
2048
1 block
BA13
LOW
I/O5
CA5
PA5
2112 bytes
BA12
LOW
I/O4
CA4
PA4
16
64
64
Micron Technology, Inc. reserves the right to change products or specifications without notice.
I/OQ3
CA11
BA11
CA3
1Gb x8, x16: NAND Flash Memory
PA3
64 pages = 1 block
1 page
1 block
1 device = (2K + 64) bytes x 64 pages
1
Device and Array Organization
I/O7
I/O0
= (2K + 64) bytes
= (2K + 64) bytes x 64 pages
= (128K + 4K) bytes
= 1056Mb
CA10
BA10
I/O2
x 1024 blocks
CA2
PA2
(128K + 4K) bytes
© 2010 Micron Technology, Inc. All rights reserved.
I/O1
CA1
CA9
PA1
BA9
I/O0
CA0
CA8
BA8
PA0

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