MT29F1G08ABADAWP-IT:D Micron Technology Inc, MT29F1G08ABADAWP-IT:D Datasheet - Page 20

• Manufacturer Part Number: MT29F1G08ABADAWP-IT:D
• Manufacturer: Micron Technology Inc

Specifications of MT29F1G08ABADAWP-IT:D

• Lead Free Status / Rohs Status: Compliant

Asynchronous Addresses
Figure 12: Asynchronous Address Latch Cycle
PDF: 09005aef83e5ffed
m68a.pdf – Rev. D 06/10 EN
WE#
ALE
I/Ox
CLE
CE#
An asynchronous address is written from I/O[7:0] to the address register on the rising
edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH.
Bits that are not part of the address space must be LOW (see Device and Array Organiza-
tion). The number of cycles required for each command varies. Refer to the command
descriptions to determine addressing requirements.
Addresses are input on I/O[7:0] on x8 devices and on I/O[15:0] on x16 devices.
t CS
t CLS
t WP
t ALS
t DS
add 1
Col
t WC
t DH
t ALH
t WH
add 2
Col
20
Asynchronous Interface Bus Operation
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Row
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb x8, x16: NAND Flash Memory
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Row
Don’t Care
© 2010 Micron Technology, Inc. All rights reserved.
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Row
Undefined