MT29F1G08ABADAWP-IT:D Micron Technology Inc, MT29F1G08ABADAWP-IT:D Datasheet - Page 30

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MT29F1G08ABADAWP-IT:D

Manufacturer Part Number
MT29F1G08ABADAWP-IT:D
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT29F1G08ABADAWP-IT:D

Lead Free Status / Rohs Status
Compliant

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Table 5: Command Set (Continued)
PDF: 09005aef83e5ffed
m68a.pdf – Rev. D 06/10 EN
Command
OTP DATA LOCK BY BLOCK
(ONFI)
OTP DATA PROGRAM (ONFI)
OTP DATA READ (ONFI)
Notes:
1. Busy means RDY = 0.
2. Do not cross plane address boundaries when using READ for INTERNAL DATA MOVE
3. These commands supported only with ECC disabled.
4. Issuing a READ PAGE CACHE series (31h, 00h-31h, 3Fh) command when the array is busy
5. Issuing a PROGRAM PAGE CACHE (80h-15h) command when the array is busy (RDY = 1,
6. OTP commands can be entered only after issuing the SET FEATURES command with the
Command
Cycle #1
and PROGRAM for INTERNAL DATA MOVE.
(RDY = 1, ARDY = 0) is supported if the previous command was a READ PAGE (00h-30h)
or READ PAGE CACHE series command; otherwise, it is prohibited.
ARDY = 0) is supported if the previous command was a PROGRAM PAGE CACHE
(80h-15h) command; otherwise, it is prohibited.
feature address.
80h
80h
00h
Number of
Address
Cycles
Valid
4
4
4
30
Cycles
Input
Data
Yes
No
No
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb x8, x16: NAND Flash Memory
Command
Cycle #2
10h
10h
30h
Command Definitions
© 2010 Micron Technology, Inc. All rights reserved.
Selected LUN is
Valid While
Busy
No
No
No
1
Notes
6
6
6

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