MT29F1G08ABADAWP-IT:D Micron Technology Inc, MT29F1G08ABADAWP-IT:D Datasheet - Page 23

• Manufacturer Part Number: MT29F1G08ABADAWP-IT:D
• Manufacturer: Micron Technology Inc

Specifications of MT29F1G08ABADAWP-IT:D

• Lead Free Status / Rohs Status: Compliant

Figure 15: Asynchronous Data Output Cycles (EDO Mode)
Write Protect#
Ready/Busy#
PDF: 09005aef83e5ffed
m68a.pdf – Rev. D 06/10 EN
RDY
I/Ox
CE#
RE#
The write protect# (WP#) signal enables or disables PROGRAM and ERASE operations
to a target. When WP# is LOW, PROGRAM and ERASE operations are disabled. When
WP# is HIGH, PROGRAM and ERASE operations are enabled.
It is recommended that the host drive WP# LOW during power-on until V
prevent inadvertent PROGRAM and ERASE operations (see Device Initialization for ad-
ditional details).
WP# must be transitioned only when the target is not busy and prior to beginning a
command sequence. After a command sequence is complete and the target is ready,
WP# can be transitioned. After WP# is transitioned, the host must wait
ing a new command.
The WP# signal is always an active input, even when CE# is HIGH. This signal should
not be multiplexed with other signals.
The ready/busy# (R/B#) signal provides a hardware method of indicating whether a tar-
get is ready or busy. A target is busy when one or more of its die (LUNs) are busy
(RDY = 0). A target is ready when all of its die (LUNs) are ready (RDY = 1). Because each
die (LUN) contains a status register, it is possible to determine the independent status
of each die (LUN) by polling its status register instead of using the R/B# signal (see Sta-
tus Operations for details regarding die (LUN) status).
This signal requires a pull-up resistor, Rp, for proper operation. R/B# is HIGH when the
target is ready, and transitions LOW when the target is busy. The signal's open-drain
t RR
t CEA
t RP
t REA
t RC
t REH
D
OUT
t RLOH
t REA
23
D
OUT
Asynchronous Interface Bus Operation
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb x8, x16: NAND Flash Memory
© 2010 Micron Technology, Inc. All rights reserved.
t RHOH
t COH
t CHZ
t RHZ
D
OUT
Don’t Care
t
WW before issu-
CC
is stable to