MT29F1G08ABADAWP-IT:D Micron Technology Inc, MT29F1G08ABADAWP-IT:D Datasheet - Page 47

• Manufacturer Part Number: MT29F1G08ABADAWP-IT:D
• Manufacturer: Micron Technology Inc

Specifications of MT29F1G08ABADAWP-IT:D

• Lead Free Status / Rohs Status: Compliant

Column Address Operations
RANDOM DATA READ (05h-E0h)
Figure 31: RANDOM DATA READ (05h-E0h) Operation
PDF: 09005aef83e5ffed
m68a.pdf – Rev. D 06/10 EN
Cycle type
I/O[7:0]
SR[6]
D
Dn
OUT
Dn + 1
D
The column address operations affect how data is input to and output from the cache
registers within the selected die (LUNs). These features provide host flexibility for man-
aging data, especially when the host internal buffer is smaller than the number of data
bytes or words in the cache register.
When the asynchronous interface is active, column address operations can address any
byte in the selected cache register.
The RANDOM DATA READ (05h-E0h) command changes the column address of the se-
lected cache register and enables data output from the last selected die (LUN). This
command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It
is also accepted by the selected die (LUN) during CACHE READ operations
(RDY = 1; ARDY = 0).
Writing 05h to the command register, followed by two column address cycles contain-
ing the column address, followed by the E0h command, puts the selected die (LUN)
into data output mode. After the E0h command cycle is issued, the host must wait at
least
mode until another valid command is issued.
OUT
t
WHR before requesting data output. The selected die (LUN) stays in data output
t
RHW
Command
05h
Address
C1
47
Address
C2
Command
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E0h
1Gb x8, x16: NAND Flash Memory
t
Column Address Operations
WHR
D
Dk
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OUT
Dk + 1
D
OUT
Dk + 2
D
OUT