Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 105
![IC 33MHZ STATIC Z180 68-PLCC](/photos/6/71/67199/269-68-plcc_sml.jpg)
Z8S18033VSG
Manufacturer Part Number
Z8S18033VSG
Description
IC 33MHZ STATIC Z180 68-PLCC
Manufacturer
Zilog
Series
Z8018xr
Specifications of Z8S18033VSG
Processor Type
Z180
Features
Enhanced Z180
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Core Size
8bit
Cpu Speed
33MHz
Digital Ic Case Style
PLCC
No. Of Pins
68
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Processor Series
Z8S180X
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
33 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8S18000ZEM
Minimum Operating Temperature
0 C
Base Number
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4307
Q2431383
Z8S18033VSG
Q2431383
Z8S18033VSG
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
Z8S18033VSG
Manufacturer:
Zilog
Quantity:
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Part Number:
Z8S18033VSG
Manufacturer:
ZILOG
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90
UM005003-0703
Z8018x
Family MPU User Manual
DMA Controller (DMAC)
3. Refresh cycles are suppressed during SLEEP mode. If a refresh cycle
4. Regarding (2) and (3), the refresh address is incremented by one for
The Z8X180 contains a two-channel DMA (Direct Memory Access)
controller which supports high speed data transfer. Both channels
(channel 0 and channel 1) feature the following capabilities:
•
•
•
is requested during SLEEP mode, the refresh cycle request is
internally latched (until replaced with the next refresh request). The
latched refresh cycle is inserted at the end of the first machine cycle
after SLEEP mode is exited. After this initial cycle, the time at which
the next refresh cycle occurs depends on the refresh time and has no
timing relationship with the exit from SLEEP mode.
each successful refresh cycle, not for each refresh request. Thus,
independent of the number of missed refresh requests, each refresh
bus cycle uses a refresh address incremented by one from that of the
previous refresh bus cycles.
Memory Address Space
Memory source and destination addresses can be directly specified
anywhere within the 1024KB physical address space using 20-bit
source and destination memory addresses. In addition, memory
transfers can arbitrarily cross 64KB physical address boundaries
without CPU intervention.
I/O Address Space
I/O source and destination addresses can be directly specified
anywhere within the 64KB I/O address space (16-bit source and
destination I/O addresses).
Transfer Length
Up to 64KB are transferred based on a 16- bit byte count register.
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