Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 120

• Manufacturer Part Number: Z8S18033VSG
• Description: IC 33MHZ STATIC Z180 68-PLCC
• Manufacturer: Zilog
• Series: Z8018xr

Specifications of Z8S18033VSG

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Core Size: 8bit
• Cpu Speed: 33MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Processor Series: Z8S180X
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 33 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8S18000ZEM
• Minimum Operating Temperature: 0 C
• Base Number: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4307; Q2431383; Z8S18033VSG

In addition, the operation of channel 0 DMA with the on-chip ASCI
(Asynchronous Serial Communication Interface) as well as Channel 1
DMA are described.
Memory to Memory—Channel 0
For memory to/from memory transfers, the external DREQ0 input is not
used for DMA transfer timing. Rather, the DMA operation is timed in one
of two programmable modes – BURST or CYCLE STEAL. In both
modes, the DMA operation automatically proceeds until termination
(shown by byte count-BCR0) =
In BURST mode, the DMA operation proceeds until termination. In this
case, the CPU cannot perform any program execution until the DMA
operation is completed. In CYCLE STEAL mode, the DMA and CPU
operation are alternated after each DMA byte transfer until the DMA is
completed. The sequence:
•
•
is repeated until DMA is completed. Figure 46 describes CYCLE STEAL
mode DMA timing.
1 CPU Machine Cycle
DMA Byte Transfer
0
.
Family MPU User Manual
UM005003-0703
Z8018x
105