Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 167

• Manufacturer Part Number: Z8S18033VSG
• Description: IC 33MHZ STATIC Z180 68-PLCC
• Manufacturer: Zilog
• Series: Z8018xr

Specifications of Z8S18033VSG

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Core Size: 8bit
• Cpu Speed: 33MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Processor Series: Z8S180X
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 33 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8S18000ZEM
• Minimum Operating Temperature: 0 C
• Base Number: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4307; Q2431383; Z8S18033VSG

152
UM005003-0703
Z8018x
Family MPU User Manual
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CSI/O Operation Timing Notes
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•
CSI/O Operation Notes
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c. Poll the RE bit in CNTR until RE =
d. Read the receive data from TRDR.
e. Repeat steps 2 to 4 for each receive data byte.
Receive–Interrupts
a. Poll the RE bit in CNTR until RE is
b. Set the RE and EIE bits in CNTR to
c. When the receive interrupt occurs read the receive data from
d. Set the RE bit in CNTR to
e. Repeat steps 3 and 4 for each receive data byte.
Transmitter clocking and receiver sampling timings are different from
internal and external clocking modes. Figure 59 to Figure 62 illustrate
CSI/O Transmit/Receive Timing.
The transmitter and receiver is disabled TE and RE
initializing or changing the baud rate.
Disable the transmitter and receiver (TE and RE =
initializing or changing the baud rate. When changing the baud rate
after completion of transmission or reception, a delay of at least one
bit time is required before baud rate modification.
When RE or TE is cleared to
or transmit operation is immediately terminated. Normally, TE or RE
is only cleared to
Simultaneous transmission and reception is not possible. Thus, TE
and RE are not both
TRDR.
0
when EF is
1
at the same time.
0
1
by software, a corresponding receive
1
.
.
0
0
1
.
.
.
0
= 0
) before
) when