Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 59
![IC 33MHZ STATIC Z180 68-PLCC](/photos/6/71/67199/269-68-plcc_sml.jpg)
Z8S18033VSG
Manufacturer Part Number
Z8S18033VSG
Description
IC 33MHZ STATIC Z180 68-PLCC
Manufacturer
Zilog
Series
Z8018xr
Specifications of Z8S18033VSG
Processor Type
Z180
Features
Enhanced Z180
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Core Size
8bit
Cpu Speed
33MHz
Digital Ic Case Style
PLCC
No. Of Pins
68
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Processor Series
Z8S180X
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
33 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8S18000ZEM
Minimum Operating Temperature
0 C
Base Number
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4307
Q2431383
Z8S18033VSG
Q2431383
Z8S18033VSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8S18033VSG
Manufacturer:
Zilog
Quantity:
40
Company:
Part Number:
Z8S18033VSG
Manufacturer:
ZILOG
Quantity:
6 252
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Table 6.
UM005003-0703
ASCI
CSI/O CSI/O Control Register
Z8018x
Family MPU User Manual
Register
ASCI Control Register A Ch 0
ASCI Control Register A Ch 1
ASCI Control Register B Ch 0
ASCI Control Register B Ch 1
ASCI Status Register Ch 0
ASCI Status Register Ch 1
ASCI Transmit Data Register Ch 0
ASCI Transmit Data Register Ch 1
ASCI Receive Data Register Ch 0
ASCI Receive Data Register Ch 1
CSI/O Transmit/Receive Data Register TRD
I/O Address Map for Z80180-Class Processors Only
address to
OTDMR and TSTIO (see Instruction Set).
When writing to an internal I/O register, the same I/O write occurs on the
external bus. However, the duplicate external I/O write cycle exhibits
internal I/O write cycle timing. For example, the WAIT input and
programmable Wait State generator are ignored. Similarly, internal I/O
read cycles also cause a duplicate external I/O read cycle. However, the
external read data is ignored by the Z8X180.
Normally, external I/O addresses should be chosen to avoid overlap with
internal I/O addresses and duplicate I/O accesses.
0
. These instructions are IN0, OUT0, OTIM, OTIMR, OTDM,
STAT0
STAT1
TDR0
CNTR
CNTLA0
CNTLA1
CNTLB0
CNTLB1
TDR1
RDR0
RDR1
Mnemonic
XX000000
XX000001
XX000010
XX000100
XX000101
XX001010
XX000011
XX000110
XX000111
XX001000
XX001001
XX1011
Binary
Address
0AH
0BH
Hex
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
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