Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 111

• Manufacturer Part Number: Z8S18033VSG
• Description: IC 33MHZ STATIC Z180 68-PLCC
• Manufacturer: Zilog
• Series: Z8018xr

Specifications of Z8S18033VSG

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Core Size: 8bit
• Cpu Speed: 33MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Processor Series: Z8S180X
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 33 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8S18000ZEM
• Minimum Operating Temperature: 0 C
• Base Number: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4307; Q2431383; Z8S18033VSG

96
UM005003-0703
Bit
Position Bit/Field R/W
6
5
4
3
2
Z8018x
Family MPU User Manual
DE0
DWE1
DWE0
DIE1
DIE0
R/W
W
W
R/W
Value
Description
Enable Channel 0 — When DE0 = 1 and DME = 1,
channel 0 DMA is enabled. When a DMA transfer
terminates BCR0 = 0), DE0: is reset to 0 by the DMAC.
When DE0 = 0 and the DMA interrupt is enabled (DIE0 =
1), a DMA interrupt request is made to the CPU.
To perform a software write to DE0, DWE0 must be written
with 0 during the same register write access. Writing DE0 to
0 disables channel 0 DMA. Writing DE0 to 1 enables
channel 0 DMA and automatically sets DME (DMA Main
Enable) to 1. DE0 is cleared to 0 during RESET.
Bit Write Enable 1 — When performing any software
write to DEI, DWE1 must be written with 0 during the
same access. DWE1 write value of 0 is not held and
DWE1 is always read as 1.
Bit Write Enable 0 — When performing any software
write to DE0, DWE0 must be written with 0 during the
same access. DWE0 write value of 0 is not held and
DWE0 is always read as 1.
DMA Interrupt Enable Channel 1 — When DIE1 is set
to 1, the termination channel 1 DMA transfer (indicated
when DE1 is 0) causes a CPU interrupt request to be
generated. When DIE1 is 0, the channel 1 DMA
termination interrupt is disabled. DIE1 is cleared to 0
during RESET.
DMA Interrupt Enable Channel 0 — When DIE0 is set
to 1, the termination channel 0 of DMA transfer
(indicated when DE0 is 0) causes a CPU interrupt request
to be generated. When DIE0 is 0, the channel 0 DMA
termination interrupt is disabled. DIE0 is cleared to 0
during RESET.