Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 96
![IC 33MHZ STATIC Z180 68-PLCC](/photos/6/71/67199/269-68-plcc_sml.jpg)
Z8S18033VSG
Manufacturer Part Number
Z8S18033VSG
Description
IC 33MHZ STATIC Z180 68-PLCC
Manufacturer
Zilog
Series
Z8018xr
Specifications of Z8S18033VSG
Processor Type
Z180
Features
Enhanced Z180
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Core Size
8bit
Cpu Speed
33MHz
Digital Ic Case Style
PLCC
No. Of Pins
68
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Processor Series
Z8S180X
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
33 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8S18000ZEM
Minimum Operating Temperature
0 C
Base Number
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4307
Q2431383
Z8S18033VSG
Q2431383
Z8S18033VSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8S18033VSG
Manufacturer:
Zilog
Quantity:
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Company:
Part Number:
Z8S18033VSG
Manufacturer:
ZILOG
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also the interrupt response sequence used for all internal interrupts
(except TRAP).
As depicted in Figure 41, the low-order byte of the vector table address
has the most significant three bits of the software programmable IL
register while the least significant five bits are a unique fixed value for
each interrupt (INT1, INT2 and internal) source:
Figure 41.
INT1 and INT2 are globally masked by IEF1 is
individually maskable by respectively clearing the ITE1 and ITE2 (bits
1,2) of the INT/TRAP control register to
During RESET, IEF1, ITE1 and ITE2 bits are reset to
Internal Interrupts
Internal interrupts (except TRAP) use the same vectored response mode
as INT1 and INT2. Internal interrupts are globally masked by IEF1 is
Individual internal interrupts are enabled/disabled by programming each
I
16-bit Vector
INT1, INT2 Vector Acquisition
IL
Fixed Code
(5 bits)
Vector + 1
Vector
of starting address
of starting address
Low-order 8 bits
High-order 8 bits
0
Family MPU User Manual
.
Memory
0
. Each is also
0
.
UM005003-0703
32 Bytes
Vector
Table
Z8018x
0
.
81
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