Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 97

• Manufacturer Part Number: Z8S18033VSG
• Description: IC 33MHZ STATIC Z180 68-PLCC
• Manufacturer: Zilog
• Series: Z8018xr

Specifications of Z8S18033VSG

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Core Size: 8bit
• Cpu Speed: 33MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Processor Series: Z8S180X
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 33 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8S18000ZEM
• Minimum Operating Temperature: 0 C
• Base Number: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4307; Q2431383; Z8S18033VSG

82
UM005003-0703
Interrupt Source
INT1
INT2
PRT channel 0
PRT channel 1
DMA channel 0
DMA channel 1
CSI/O
ASCI channel 0
ASCI channel 1
Z8018x
Family MPU User Manual
Interrupt Acknowledge Cycle Timings
individual I/O (PRT, DMAC, CSI/O, ASCI) control register. The lower
vector of INT1 INT2 and internal interrupt are summarized in Table 9.
Table 9.
Figure 43 illustrates INT1, INT2, and internal interrupts timing. INT1 and
INT2 are sampled at the falling edge of the clock state prior to T2 or T1 in
the last machine cycle. If INT1 or INT2 is asserted Low at the falling
edge of clock state prior to T3 or T1 in the last machine cycle, the
interrupt request is accepted.
Priority
Highest
Lowest
Vector Table
—
—
—
—
—
—
IL
b7
—
—
—
b6
—
—
—
—
—
—
—
—
—
b5
—
—
—
—
—
—
—
—
—
Fixed Code
b4
0
0
0
0
0
0
0
0
1
b3
0
0
0
0
1
1
1
1
0
b2
0
0
1
1
0
0
1
1
0
b1
0
1
0
1
0
1
0
1
0
b0
0
0
0
0
0
0
0
0
0