Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 84
Z8S18033VSG
Manufacturer Part Number
Z8S18033VSG
Description
IC 33MHZ STATIC Z180 68-PLCC
Manufacturer
Zilog
Series
Z8018xr
Specifications of Z8S18033VSG
Processor Type
Z180
Features
Enhanced Z180
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Core Size
8bit
Cpu Speed
33MHz
Digital Ic Case Style
PLCC
No. Of Pins
68
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Processor Series
Z8S180X
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
33 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8S18000ZEM
Minimum Operating Temperature
0 C
Base Number
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4307
Q2431383
Z8S18033VSG
Q2431383
Z8S18033VSG
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If IEF1 is
the DI (Disable Interrupts) instruction and set to
Interrupts) instruction.
The purpose of IEF2 is to correctly manage the occurrence of NMI.
During NMI, the prior interrupt reception state is saved and all maskable
interrupts are automatically disabled (IEF1 copied to IEF2 and then IEF1
cleared to
the RETN (Return from Non-maskable Interrupt) automatically restores
the interrupt receiving state (by copying IEF2 to IEF1) prior to the
occurrence of NMI.
Table 8 describes how the IEF2 state can be reflected in the P/V bit of the
CPU Status Register by executing LD A, I or LD A, R instructions.
Table 8.
CPU
Operation
RESET
NMI
RETN
Interrupt except
NMI end TRAP
RETI
TRAP
EI
0
0
State of IEF1 and IEF2
, all maskable interrupts are disabled. IEF1 can be reset to
). At the end of the NMI interrupt service routine, execution of
IEF1
0
0
IEF2
0
not affected not affected
not affected not affected
1
IEF2
0
IEF1
not affected Returns from the NMI service
0
1
Family MPU User Manual
REMARKS
Inhibits the interrupt except NMI
and TRAP.
Copies the contents of IEF1 to
IEF2
routine.
Inhibits the interrupt except NMI
end TRAP
1
by the El (Enable
UM005003-0703
Z8018x
0
by
69
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