Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 48
![IC 33MHZ STATIC Z180 68-PLCC](/photos/6/71/67199/269-68-plcc_sml.jpg)
Z8S18033VSG
Manufacturer Part Number
Z8S18033VSG
Description
IC 33MHZ STATIC Z180 68-PLCC
Manufacturer
Zilog
Series
Z8018xr
Specifications of Z8S18033VSG
Processor Type
Z180
Features
Enhanced Z180
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Core Size
8bit
Cpu Speed
33MHz
Digital Ic Case Style
PLCC
No. Of Pins
68
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Processor Series
Z8S180X
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
33 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8S18000ZEM
Minimum Operating Temperature
0 C
Base Number
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4307
Q2431383
Z8S18033VSG
Q2431383
Z8S18033VSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8S18033VSG
Manufacturer:
Zilog
Quantity:
40
Company:
Part Number:
Z8S18033VSG
Manufacturer:
ZILOG
Quantity:
6 252
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INT1, NMI
.
A0
Figure 20.
SLEEP Mode
SLEEP mode is entered by execution of the 2-byte SLP instruction.
SLEEP mode contains the following characteristics:
•
•
•
•
•
•
•
•
MREQ
HALT
–
A19
The internal CPU clock stops, reducing power consumption
The internal crystal oscillator does not stop
Internal and external interrupt inputs can be received
DRAM refresh cycles stop
I/O operations using on-chip peripherals continue
The internal DMAC stop
BUSREQ can be received and acknowledged
Address outputs go High and all other control signal outputs become
inactive High
Phi
RD
M1
HALT Op Code address
HALT Timing Diagram
T1
HALT Op Code
Fetch Cycle
T3
T1
HALT mode
HALT Op Code address + 1
T2
Family MPU User Manual
T3
T1
Interrupt
acknowledge cycle
UM005003-0703
Z8018x
T2
33
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