Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 106

• Manufacturer Part Number: Z8S18033VSG
• Description: IC 33MHZ STATIC Z180 68-PLCC
• Manufacturer: Zilog
• Series: Z8018xr

Specifications of Z8S18033VSG

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Core Size: 8bit
• Cpu Speed: 33MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Processor Series: Z8S180X
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 33 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8S18000ZEM
• Minimum Operating Temperature: 0 C
• Base Number: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4307; Q2431383; Z8S18033VSG

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There is an additional feature disc for DMA interrupt request by DMA
END. Each channel has the following additional specific capabilities:
Channel 0
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Channel 1
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DMAC Registers
Each channel of the DMAC (channel 0, 1) contains three registers
specifically associated with that channel.
DREQ Input
Level- and edge-sense DREQ input detection are selectable.
TEND Output Used to indicate DMA completion to external devices.
Transfer Rate
Each byte transfer occurs every 6 clock cycles. Wait States can be
inserted in DMA cycles for slow memory or I/O devices. At the
system clock (f) = 6 MHz, the DMA transfer rate is as high as 1.0
megabytes/second (no Wait States).
Memory to memory
Memory to I/O
Memory to memory mapped I/O transfers.
Memory address increment, decrement, no-change
Burst or cycle steal memory to/from memory transfers
DMA to/from both ASCI channels
Higher priority than DMAC channel 1
Memory to/from I/O transfer
Memory address increment, decrement
Family MPU User Manual
UM005003-0703
Z8018x
91