Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 177

• Manufacturer Part Number: Z8S18033VSG
• Description: IC 33MHZ STATIC Z180 68-PLCC
• Manufacturer: Zilog
• Series: Z8018xr

Specifications of Z8S18033VSG

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Core Size: 8bit
• Cpu Speed: 33MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Processor Series: Z8S180X
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 33 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8S18000ZEM
• Minimum Operating Temperature: 0 C
• Base Number: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4307; Q2431383; Z8S18033VSG

162
UM005003-0703
Bit
Position Bit/Field R/W
7
5
3
1
–
–
–
–
Z8018x
Family MPU User Manual
6
4
2
0
TIF1
TIE1
TOC1
TDE1
–
–
–
–
0
0
0 R/W
0 R/W
R
R/W
Value
Description
TIF1: Timer Interrupt Flag — When TMDR1
decrements to 0, TIF1 is set to 1. This generates an
interrupt request if enabled by TIE1 = 1. TIF1 is reset to 0
when TCR is read and the higher or lower byte of
TMDR1 is read. During RESET, TIF1 is cleared to 0.
When TMDR0 decrements to 0, TIF0 is set to 1. This
generates an interrupt request if enabled by TIE0 = 1.
TIF0 is reset to 0 when TCR is read and the higher or
lower byte of TMDR0 is read. During RESET, TIF0 is
cleared to 0.
Timer Interrupt Enable — When TIE1 is set to 1, TIF1
= 1 generates a CPU interrupt request. When TIE1 is reset
to 0, the interrupt request is inhibited. During RESET,
TIE1 is cleared to 0.
When TIE0 is set to 1, TIF0 = 1 generates a CPU interrupt
request. When TIE0 is reset to 0, the interrupt request is
inhibited. During RESET, TIE0 is cleared to 0.
Timer Output Control — TOC1, and TOC0 control the
output of PRT1 using the multiplexed A18/TOUT pin as
shown in Table 23. During RESET, TOC1 and TOC0 are
cleared to 0. This selects the address function for A18/
TOUT. By programming TOC1 and TOC0 the A18/
TOUT pin can be forced HIGH, LOW, or toggled when
TMDR1 decrements to 0. Reference Table 23.
Timer Down Count Enable — TDE1 and TDE0 enable
and disable down counting for TMDR1 and TMDR0
respectively. When TDEn (n = 0, 1) is set to 1, down
counting is executed for TMDRn. When TDEn is reset to
0, down counting is stopped and TMDRn is freely read or
written. TDE1 and TDE0 are cleared to 0 during RESET
and TMDRn does not decrement until TDEn is set to 1.