Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 161
![IC 33MHZ STATIC Z180 68-PLCC](/photos/6/71/67199/269-68-plcc_sml.jpg)
Z8S18033VSG
Manufacturer Part Number
Z8S18033VSG
Description
IC 33MHZ STATIC Z180 68-PLCC
Manufacturer
Zilog
Series
Z8018xr
Specifications of Z8S18033VSG
Processor Type
Z180
Features
Enhanced Z180
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Core Size
8bit
Cpu Speed
33MHz
Digital Ic Case Style
PLCC
No. Of Pins
68
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Processor Series
Z8S180X
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
33 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8S18000ZEM
Minimum Operating Temperature
0 C
Base Number
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4307
Q2431383
Z8S18033VSG
Q2431383
Z8S18033VSG
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Part Number:
Z8S18033VSG
Manufacturer:
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UM005003-0703
Z8018x
Family MPU User Manual
Clocked Serial I/O Port (CSI/O)
causes for an ASCI Receive interrupt (PE, FE, OVRN, and for ASCI0,
DCD) continue to request RX interrupt if the RIE bit is 1. The Rx DMA
request is inhibited if PE or FE or OVRN is set, so that software can
detect where an error occurred. When the RIE bit is 0, as it is after a
Reset, RDRF causes an ASCI interrupt if RIE is 1.
The Z8X180 includes a simple, high-speed clock, synchronous serial I/O
port. The CSI/O includes transmit/receive (half-duplex), fixed 8-bit data,
and internal or external data clock selection. High-speed operation (baud
rate 200Kbps at fC = 4 MHz) is provided. The CSI/O is ideal for
implementing a multiprocessor communication link between multiple
Z8X180s. These secondary devices may typically perform a portion of the
system I/O processing, (that is, keyboard scan/decode, LDC interface, for
instance).
CSI/O Block Diagram
The CSI/O block diagram is illustrated in Figure 57. The CSI/O consists
of two registers–the Transmit/Receive Data Register (TRDR) and Control
Register (CNTR).
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