PSB2186N-V11TR Infineon Technologies, PSB2186N-V11TR Datasheet - Page 118

• Manufacturer Part Number: PSB2186N-V11TR
• Description: IC ISDN SUBSCRIB ACCESS 44-PLCC
• Manufacturer: Infineon Technologies

Specifications of PSB2186N-V11TR

• Controller Type: Subscriber Access Controller (ISDN)
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 17mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: PSB2186N-V11INTR; PSB2186N-V11TR

Operational Description
A read of the ISTA register clears all bits except EXI and CISQ. CISQ is cleared by reading
CIR0. A read of EXIR clears the EXI bit in ISTA as well as the EXIR register.
When all bits in ISTA are cleared, the interrupt line (INT) is deactivated.
Each interrupt source in ISTA register can be selectively masked by setting to "1" the
corresponding bit in MASK. Masked interrupt status bits are not indicated when ISTA is read.
Instead, they remain internally stored and pending, until the mask bit is reset to zero. Reading
the ISTA while a mask bit is active has no effect on the pending interrupt.
In the event of an extended interrupt and of a C/I- or S/Q channel change, EXI and CISQ are
set even when the corresponding mask bits in MASK are active, but no interrupt (INT) is
generated.
Except for CISQ and MOS all interrupt sources are directly determined by a read of ISTA and
(possibly) EXIR.
CISQ-Interrupt Logic
– A CISQ interrupt may originate
– from a change in the received S/Q code (SQC)
– from a change in the received C/I channel 0 code (CIC0)
or (in the case of IOM-2 terminal mode only)
– from a change in the received C/I channel 1 code (CIC1).
The three corresponding status bits SQC, CIC0 and CIC1 are read in the CIR0 register. SQC
and CIC1 can be individually disabled by clearing the enable bit SQIE (SQXR register) or,
respectively, CI1E (SQXR register). In this case the occurrence of a code change in SQRR/
CIR1 will not be displayed by SQC/CIC1 until the corresponding enable bit has been set to one.
Bits SQC, CIC0 and CIC1 are cleared by a read of CIR0.
An interrupt status is indicated every time a valid new code is loaded in SQRR, CIR0 or CIR1.
But in case of a code change, the new code is not loaded until the previous contents have been
read. When this is done and a second code change has already occurred, a new interrupt is
immediately generated and the new code replaces the previous one in the register. The code
registers are buffered with a FIFO size of two. Thus, if several consecutive codes are detected,
only the first and the last code is obtained at the first and second register read, respectively.
Semiconductor Group
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