PSB2186N-V11TR Infineon Technologies, PSB2186N-V11TR Datasheet - Page 58

• Manufacturer Part Number: PSB2186N-V11TR
• Description: IC ISDN SUBSCRIB ACCESS 44-PLCC
• Manufacturer: Infineon Technologies

Specifications of PSB2186N-V11TR

• Controller Type: Subscriber Access Controller (ISDN)
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 17mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: PSB2186N-V11INTR; PSB2186N-V11TR

Table 4
Priority Commands/Indications
Command (upstream)
Activate request, set priority 8
Activate request, set priority 10
Indication (downstream)
Activate indication with priority
class 8
Activate indication with priority
class 10
2.4.9
Access to the received/transmitted S- or Q channel is provided via registers. As specified by
CCITT I.430, the Q bit is transmitted from TE to NT in the position normally occupied by the
auxiliary framing bit (F
in a spare bit, see figure 22.
The functions provided by the ISAC-S are:
– Synchronization to the received 20 frame multiframe by means of the received M bit pattern.
– When synchronism is achieved, the four received S bits in frames 1, 6, 11 and 16 are stored
– When an M bit is observed to have a value different from that expected, the synchronism is
– When synchronism with the received multiframe is achieved, the four bits SQX1 to SQX4
– The S/T multiframe synchronization can be disabled in the STAR2 register (MULT bit).
Semiconductor Group
Synchronism is achieved when the M bit has been correctly received during 20 consecutive
frames starting from frame number 1 (table 5).
as SQR1 to SQR4 in the SQRR register if the complete M bit multiframe pattern was
correctly received in the corresponding multiframe. A change in any of the received four bits
(SQR1, 2, 3 or 4) is indicated by an interrupt (CISQ in ISTA and SQC in CIR0).
considered lost. The SQR bits are not updated until synchronism is regained. The
synchronization state is constantly indicated by the SYN bit in the SQRR register.
stored in the SQXR register are transmitted as the four Q bits (F
6, 11 and 16 respectively (starting from frame number one). Otherwise the bit transmitted is
a mirror of the received F
resumed starting with the next F
S- and Q-Channel Access
A
) in one frame out of 5, whereas the S bit is transmitted from NT to TE
A
-bit. At loss of synchronism (mismatch in M bit) the mirroring is
Abbr.
AR8
AR10
Abbr.
AI8
AI10
A
-bit.
Code
1000
1001
Code
1100
1101
58
Remarks
Activation command: Set D-channel
priority to 8
Activation command: Set D-channel
priority to 10
Remarks
Info 4 received: D-channel priority is 8
or 9
Info 4 received: D-channel priority is
10 or 11
Functional Description
A
-bit position) in frames 1,