PSB2186N-V11TR Infineon Technologies, PSB2186N-V11TR Datasheet - Page 191

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PSB2186N-V11TR

Manufacturer Part Number
PSB2186N-V11TR
Description
IC ISDN SUBSCRIB ACCESS 44-PLCC
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB2186N-V11TR

Controller Type
Subscriber Access Controller (ISDN)
Interface
4-Wire SPI Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
17mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
PSB2186N-V11INTR
PSB2186N-V11TR
Jitter
In TE mode, the timing extraction jitter of the ISAC-S conforms to CCITT Recommendation
I.430 (– 7 % to + 7 % of the S-interface bit period).
Description of the Receive PLL (RPLL) of the ISAC-S TE
The receive PLL performs phase tracking each 250 s after detecting the phase between the
F/L transition of the receive signal and the recovered clock. Phase adjustment is done by
adding or subtracting 130 ns to or form a 1.536-MHz clock cycle. The 1.536-MHz clock is than
used to generate any other clock synchronized to the line.
During (re)synchronization an internal reset condition may effect the 1.536-MHz clock to have
high or low times as short as 130 ns. After the S/T-interface frame has achieved the
synchronized state (after three consecutive valid pairs of code violations) the FSC output is set
to a specific phase relationship, thus causing once an irregular FSC timing.
Reset
Table 23
Reset Signal Characteristics
Parameter
Length of active
high state
Figure 71
Reset
Semiconductor Group
RST
Symbol
t
RST
Limit Values
min.
4
2 x DCL
clock cycles
191
t
RST
Unit
ms
Electrical Characteristics
Test Condition
Power-on/Power-Down
to Power-Up (Standby)
During Power-Up (Standby)
ITD02396

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