PSB2186N-V11TR Infineon Technologies, PSB2186N-V11TR Datasheet - Page 165

• Manufacturer Part Number: PSB2186N-V11TR
• Description: IC ISDN SUBSCRIB ACCESS 44-PLCC
• Manufacturer: Infineon Technologies

Specifications of PSB2186N-V11TR

• Controller Type: Subscriber Access Controller (ISDN)
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 17mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: PSB2186N-V11INTR; PSB2186N-V11TR

CIC1
Note:
4.2.3
Value after reset:
RSS
BAC
Semiconductor Group
C/I Code 1 Change
A change in the received Command/Indication code in IOM channel 1 has been rec-
ognized. This bit is set when a new code is detected in one IOM frame. It is reset by
a read of CIR0.
CIC1 is only used if terminal mode is selected.
The BAS and CODR0 bits are updated every time a new C/I code is detected in two
consecutive IOM frames.
If several consecutive valid new codes are detected and CIR0 is not read, only the
first and the last C/I code (and BAS bit) is made available in CIR0 at the first and sec-
ond read of that register, respectively.
7
Reset Source Select
Only valid if the terminal specific functions are activated (STCR:TSF).
0:
1:
Bus Access Control
Only valid if the TIC-bus feature is enabled (MODE:DIM2-0).
If this bit is set, the ISAC-S TE will try to access the TIC bus to occupy the C/I channel
even if no D-channel frame has to be transmitted. It should be reset when the access
has been completed to grant a similar access to other devices transmitting in that IOM
channel.
Command/Indication Transmit 0
RSS
Subscriber or Exchange Awake
As reset source serves:
– a falling edge on the EAW line (External Subscriber Awake)
– a C/I code change (Exchange Awake).
A logical zero on the EAW line activates also the IOM-interface clock and frame
signal, just as the SPU-bit (SPCR) does.
Watchdog Timer
The expiration of the watchdog timer generates a reset pulse.
The watchdog timer will be reset and restarted, when two specific bit
combinations are written in the ADF1 register within the time period of 128 ms
(see also ADF1 register description).
After a reset pulse generated by the ISAC-S TE and the corresponding interrupt
(WOV, SAW or CISQ) the actual reset source can be read from the ISTA and
EXIR register.
3F
BAC
H
CODX0
165
CIX0
Write
1
Register Description
1
Address 31
0
H