PSB2186N-V11TR Infineon Technologies, PSB2186N-V11TR Datasheet - Page 72

• Manufacturer Part Number: PSB2186N-V11TR
• Description: IC ISDN SUBSCRIB ACCESS 44-PLCC
• Manufacturer: Infineon Technologies

Specifications of PSB2186N-V11TR

• Controller Type: Subscriber Access Controller (ISDN)
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 17mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: PSB2186N-V11INTR; PSB2186N-V11TR

Functional Description
If a 2-byte address field has been selected, the ISAC-S TE takes the contents of the XAD 1
register to build the high byte of the address field, and the contents of the XAD 2 register to
build the low byte of the address field.
Additionally the C/R bit (bit 1 of the high byte address, as defined by LAPD protocol) is set to
"1" or "0" dependent on whether the frame is a command or a response.
In the case of a 1 byte address, the ISAC-S TE takes either the XAD 1 or XAD 2 register to
differentiate between command or response frame (as defined by X.25 LAPB).
The control field is also generated by the ISAC-S TE including the receive and send sequence
number and the poll/final (P/F) bit. For this purpose, the ISAC-S TE internally manages send
and receive sequence number counters.
In the auto-mode, S frames are sent autonomously by the ISAC-S TE. The transmission of U
frames, however, must be done by the CPU. U frames must be sent as transparent frames
(CMDR:XTF), i.e. address and control field must be defined by the CPU.
Once the data transmission has been initiated by command (CMDR:XTF or XIF), the data
transfer between CPU and the ISAC-S TE is controlled by interrupts.
The ISAC-S TE repeatedly requests another data packet or block by means of an ISTA:XPR
interrupt, every time no more than 32 bytes are stored in the XFIFO.
The processor can then write further data to the XFIFO and enable the continuation of frame
transmission by issuing an XIF/XTF command.
If the data block which has been written last to the XFIFO completes the current frame, this
must be indicated additionally by setting the XME (Transmit Message End) command bit. The
ISAC-S TE then terminates the frame properly by appending the CRC and closing flag.
If the CPU fails to respond to an XPR interrupt within the given reaction time, a data underrun
condition occurs (XFIFO holds no further valid data). In this case, the ISAC-S TE automatically
aborts the current frame by sending seven consecutive "ones" (ABORT sequence).
The CPU is informed about this via an XDU (Transmit Data Underrun) interrupt.
It is also possible to abort a message by software by issuing a CMDR:XRES (Transmitter
RESet) command, which causes an XPR interrupt.
After an end of message indication from the CPU (CMDR:XME command), the termination of
the transmission operation is indicated differently, depending on the selected message
transfer mode and the transmitted frame type.
If the ISAC-S TE is operating in the auto mode, the window size (= number of outstanding
unacknowledged frames) is limited to "1"; therefore an acknowledgement is expected for every
I frame sent with an XIF command. The acknowledgement may be provided either by a
received S or I frame with corresponding receive sequence number.
If no acknowledgement is received within a certain time (programmable), the ISAC-S TE
requests an acknowledgement by sending an S frame with the poll bit set (P = 1) (RR or RNR).
If no response is received again, this process is repeated in total N2 times (retry count,
programmable via TIMR register).
Semiconductor Group
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