PSB2186N-V11TR Infineon Technologies, PSB2186N-V11TR Datasheet - Page 119

• Manufacturer Part Number: PSB2186N-V11TR
• Description: IC ISDN SUBSCRIB ACCESS 44-PLCC
• Manufacturer: Infineon Technologies

Specifications of PSB2186N-V11TR

• Controller Type: Subscriber Access Controller (ISDN)
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 17mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: PSB2186N-V11INTR; PSB2186N-V11TR

Operational Description
MOS-Interrupt Logic
The MONITOR Data Receive (MDR) and the MONITOR End of Reception (MER) interrupt
status bits have two enable bits, MONITOR Receive interrupt Enable (MRE) and MR bit
Control (MRC). The MONITOR channel Data Acknowledged (MDA) and MONITOR channel
Data Abort (MAB) interrupt status bits have a common enable bit MONITOR Interrupt Enable
(MXE).
MRE prevents the occurrence of the MDR status, including when the first byte of a packet is
received. When MRE is active (1) but MRC is inactive, the MDR-interrupt status is generated
only for the first byte of a receive packet. When both MRE and MRC are active, MDR is
generated and all received monitor bytes – marked by a 1-to-0 transition in MX bit – are stored.
(Additionally, an active MRC enables the control of the MR handshake bit according to the
MONITOR channel protocol.)
Control of Edge-Triggered Interrupt Controllers
The INT output is level active. It stays active until all interrupt sources have been serviced. If
a new status bit is set while an interrupt is serviced, the INT line stays active. This may cause
problems if the ISAC-S TE is connected to edge-triggered interrupt controllers (figure 43).
To avoid these problems, it is recommended to mask all interrupts at the end of the interrupt
service program and to enable the interrupts again. This is done by writing FF
to the MASK
H
register and to write back the old value of the MASK register (figure 44).
Semiconductor Group
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