PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 109

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 10-6:
FIGURE 10-7:
 2005 Microchip Technology Inc.
Note 1:
Note 1:
2:
3:
2:
I/O pin has diode protection to V
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
For PIC18F8525/8621 parts, the ECCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0)
in the Configuration register and the device is operating in Microprocessor, Microprocessor with Boot Block or
Extended Microcontroller mode.
I/O pins have diode protection to V
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
RBPU
Data Bus
RD TRISB
RD LATB
RD PORTB
BLOCK DIAGRAM OF RB2:RB0 PINS
BLOCK DIAGRAM OF RB3 PIN
CCP2MX
ECCP Output
Enable
ECCP Output
WR LATB or
WR PORTB
WR TRISB
RD PORTB
ECCP2 or INT3
(2)
(3)
Data Bus
INTx
RBPU
WR TRISB
RD TRISB
RD PORTB
WR LATB or
WR PORTB
(3)
Schmitt Trigger
Buffer
(2)
TRIS Latch
Data Latch
D
D
CK
CK
DD
PIC18F6525/6621/8525/8621
Q
Q
Data Latch
TRIS Latch
and V
CCP2MX = 0
D
D
CK
CK
DD
Schmitt Trigger
Buffer
and V
SS
Q
Q
Q
1
0
.
SS
EN
.
D
Q
EN
TTL
Input
Buffer
D
V
P
RD Port
DD
Weak
Pull-up
I/O pin
V
V
N
P
SS
DD
(1)
TTL
Input
Buffer
V
P
DD
Weak
Pull-up
I/O pin
(1)
DS39612B-page 107