PIC18F6621-I/PT Microchip Technology Inc., PIC18F6621-I/PT Datasheet - Page 113

• Manufacturer Part Number: PIC18F6621-I/PT
• Description: 64 PIN, 64 KB FLASH, 3840 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6621-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 54
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 3.8K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

10.4
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register, read and write the latched output value for
PORTD.
PORTD is an 8-bit port with Schmitt Trigger input
buffers. Each pin is individually configurable as an input
or output.
PORTD is multiplexed with the system bus as the
external memory interface. I/O port functions are only
available when the system bus is disabled by setting
the
(MEMCON<7>). When operating as the external
memory interface, PORTD is the low-order byte of the
multiplexed address/data bus (AD7:AD0).
PORTD can also be configured as an 8-bit wide
microprocessor port (Parallel Slave Port) by setting
control bit PSPMODE (TRISE<4>). In this mode, the
input buffers are TTL. See Section 10.10 “Parallel
Slave Port” for additional information on the Parallel
Slave Port (PSP).
EXAMPLE 10-4:
 2005 Microchip Technology Inc.
CLRF
CLRF
MOVLW
MOVWF
Note:
EBDIS
PORTD, TRISD and LATD
Registers
PORTD
LATD
0xCF
TRISD
On a Power-on Reset, these pins are
configured as digital inputs.
bit
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
in
INITIALIZING PORTD
the
MEMCOM
PIC18F6525/6621/8525/8621
register
FIGURE 10-9:
RD TRISD
RD PORTD
RD LATD
Data
Bus
WR TRISD
Note 1:
WR LATD
or
PORTD
I/O pins have diode protection to V
TRIS Latch
Data Latch
D
D
CK
CK
PORTD BLOCK DIAGRAM
IN I/O PORT MODE
Q
Q
Q
EN
DS39612B-page 111
EN
Schmitt
Trigger
Input
Buffer
D
DD
and V
SS
I/O pin
.
(1)